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ADS5296A: Full scale ramp test pattern output format

NR_92
Prodigy 60 points
Part Number: ADS5296A

Hi,

I'm currently writing firmware to interface this device to an FPGA in 10 bit mode. At the minute I can read full scale ramp test pattern data into the FPGA from the ADC. However, It seems I have work to do to get the data through my SERDES into the FPGA fabric in the correct order. From the data that I receive from the ADC, it looks like the full scale ramp test pattern data increments in counts of four. There could be many reasons for this on my side of the design but first I would like to be sure of exactly how the full scale ramp test pattern data is output. So my question is...

Does anyone know for sure what the value of the incremental count of the full scale ramp test pattern should be when the ADC is configured for 10 bit mode?

For 12 bit mode I can see from the user manual (slau537 , pg27, fig.35) that the full scale ramp test pattern should increment in steps of 1. There seems to be no information provided for 10 bit mode.

Thanks in advance,

Niall

  • 0
    TI__Genius 12025 points
    Hi Niall,
    How are you?
    Thanks for using ADS5296A device.
    I will look into your question.

    Thank you!
    Best regards,
    Chen
  • 0 in reply to Chen Kung
    Prodigy 60 points

    Hi Chen,

    Very well thanks, looking forward to your answer.

    Thanks,

    Niall

  • 0 in reply to NR_92
    TI__Genius 12025 points
    Hi Niall,
    How are you?
    When you were setting the ADS5296A register to run the RAMP pattern,
    did you set the Register Address=0x25, Data=0x0040
    is it correct?
    If it is correct, could you please also check if you have the following setting as well:
    1) for setting 12bit mode, please set Register Address=0x46, Data=0x8200
    1) for setting 10bit mode, please set Register Address=0x46, Data=0x8100

    Hope this setting can help.

    Thank you!
    Best regards,
    Chen
  • 0 in reply to Chen Kung
    Prodigy 60 points

    Hi Chen,

    Yes I am setting both registers 25 to 0x0040 and 46 to 0x8100.

    I am confident that the device is configured correctly. I have successfully confirmed that the device is in 10 bit serialization mode via oscilloscope. Also the device is definatley outputting repeating ramp test pattern data.

    I would like to know the value of the full scale ramp test pattern increments when the device is configured for 10 bit serialization mode. Can you ask the design team for this information?

    Thanks,

    Niall

  • 0 in reply to NR_92
    TI__Genius 12025 points
    Hi Niall,

    Thanks for letting me know.
    Yes, you are settings are correct.
    Also the full scale ramp pattern should show you:
    1) when you setup to 10bit mode register, the captured ramp pattern supposed to output from code0 to code1023.
    2) when you setup to 12bit mode register, the captured ramp pattern supposed to output from code0 to code4095.
    Both cases would only increase one code for each captured sample.

    I will ask our system engineer for your concern.
    Thank you!

    Best regards,
    Chen
  • 0 in reply to Chen Kung
    TI__Genius 12025 points

    Hi Niall,

    How are you?

    Please confirm with us that you are using ADS5296A EVM and TSW1400EVM on your test bench

    to run Full scale ramp test pattern.

    The data test results are captured from using TSW1400 GUI

    (of course including setting all the ADS5296A registers correctly.) right?

    If those conditions are correct, then please use the following

    two .ini files (one is used for 10bit mode, the other one for 12bit mode)

    needed to be loaded to under your computer's HSDC Pro file directory as:

    C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\1400 Details\ADC files

    Please save these two files inside.

    After that, please at first Exit your HSDC Pro GUI

    and then re-Run that HSDC Pro GUI again.

    When it asks you to "Select ADC ini file"

    please choose one of the files I sent to you according to your need.

    Hope they can help you to run and capture ADS5296A EVM correctly again.

    Thank you very much.

    Best regards,

    Chen

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/73/ADS5296A_5F00_10b_5F00_8ch_2800_to_5F00_Niall_2900_.ini

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/73/ADS5296A_5F00_12b_5F00_8ch_2800_to_5F00_Niall_2900_.ini

  • 0 in reply to Chen Kung
    Prodigy 60 points

    Hi Chen,

    No I am not using an evaluation board.

    The device is placed in our own hardware.

    Where you able to confirm with the system engineer that the full scale ramp pattern in 10bit serialisation mode should increment in steps of 1?

    Thank you.

    Niall.

  • 0 in reply to NR_92
    TI__Genius 12025 points
    Hi Niall,

    How are you?
    We are using TSW1400EVM to capture the ADS5296A output data.
    Also we already verified using both 10bit mode and 12bit mode register setting
    and received the output data using TSW1400EVM and GUI.
    Both show the full scale ramp patterns (in both bit modes)
    are showing the increment in step of 1.
    Since you are using the different capture FPGA
    which can not be characterized by us.
    So please re-setup the following register settings for ADS5296A device as followings
    before you will be capturing the output data from your own FPGA:
    Please make sure to set:
    Addr=0x00, Data=0x0001
    Addr=0x00, Data=0x0000
    Addr=0xBE, Data=0x80B3
    Addr=0x40, Data=0x8000
    Addr=0x46, Data=0x8200
    Addr=0x46, Data=0x8100
    Addr=0x45, Data=0x0000
    Addr=0x25, Data=0x0040

    Hope this can help you capture the full scale ramp pattern data correctly.
    Thank you!

    Best regards,
    Chen
  • 0 in reply to Chen Kung
    Prodigy 60 points

    Hi Chen,

    Ok thanks, this answer my question. Now that I know what to expect from the output pattern I can look for the issue.

    I will write the values mentioned to the registers next week and see if there is any change but the problem likely is my firmware.

    Thanks for your help.

    Niall