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LM98640QML-SP: LVDS timing

Bradley Harden
Prodigy 160 points
Part Number: LM98640QML-SP


Hi,

The datasheet provides LVDS timing specifications at an INCLK frequency of 40 MHz. Do you have any data at other INCLK frequencies? I would expect the timing requirements to be relaxed at lower frequencies. Is that correct? Do you have any specifications?

Also, can I assume that the LVDS output clock (TXCLK) is 50% duty cycle? I don't see that explicitly stated anywhere. If so, is that guaranteed? In quad lane mode, it figures into calculations for the falling edge setup time and the rising edge hold time.

Thanks,

Bradley

  • 0
    TI__Genius 14540 points
    Timing specs are typically provided at the fastest clock frequencies as these specs become relaxed when the frequency slows. No other specifications are provided.

    Yes, the LVDS output clock is 50% or very close to it by design. This is not specified in the datasheet.

    Thanks
    Christian