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ADC128S102QML-SP: Glitches on CS/ during conversion

Kenneth Pham
Prodigy 80 points
Part Number: ADC128S102QML-SP

Will CS/ going momentarily HIGH due to glitches in the middle of an ongoing conversion reset everything and restart a new reading? In this case, the data being read will be incorrect? 

  • 0
    TI__Genius 17125 points

    Hello Kenneth,

    Yes, a glitch on CSb will cause a reset of the state machine and the conversion cycle will start over.  

    Also, you need 16 full clock cycles or the registers will not be updated and the correct channel will not be choosen for the next conversion cycle.   Which channel is sompled is random upon startup.   If you have have glitches in your first conversion cycles, the channel being sampled will be unknown.  

    If you are in continuous capture mode and have a glich on CSb, a new sample and hold and conversion cycle will start when CSb goes low.   From there, the output will be valid.