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ADS1218: Query regarding the External clock

MAKESH KANNAA P G
Prodigy 80 points
Part Number: ADS1218

Hi Team,

I am using ADS1218Y with a external clock of frequency - 2.4576MHz/ Amplitude - 4Vpp from a function generator. I was able to successfully use all functions like registers,ram, flash ADC,DAC etc

I want to know the minimum and maximum limit for amplitude of the external clock.In datasheet, frequency limits(1 MHz to 5 MHz) are mentioned but not the amplitude.

Please let me know the amplitude limit for the external clock of ADS1218Y.

Note:-

I am using AVdd = DVdd = 5V. Fdata = 10Hz. 

Thanks and Regards,

Makesh

  • 0
    TI__Guru**** 181021 points
    Hi Makesh,

    There is a table on page 2 of the datasheet that lists the ABS MAX voltage that you can apply to the ADS1218. In short, you can't exceed AVdd or DVdd on any input by more than 300 mV, so that sets the amplitude limit for the external clock.
  • 0 in reply to Tom Hendrick
    Prodigy 80 points

    Hi Tom,

    Thanks for the response!

    It is understood that the maximum limit for amplitude of external clock is DVdd/AVdd + 0.3V. Could you please let me know the lower limit of the amplitude of the external clock.

    I am using the ADS1218Y at external clock frequency 2.4576MHz at the amplitude of 2Vp(i.e., Square wave varying from 0V to 2V) and DVdd = 5V. I could able to do all functions with this configuration.

    But when increasing the amplitude of the external clock to 5V(i.e., Square wave varying from 0V to 5V). I am facing issues in ADC functions. The output values differs from the input by approx 100mV.

    I use the below config,

    PGA = 1, Vref = 2.5V(Internal), Fdata = 10Hz. SCLK = 1KHz. 

    Please let me know if any more details is needed.

    In the Datasheet at page no.7, table - Digital characteristics, it is mentioned VIH should be between 0.8*DVdd and DVdd. Does it apply to the amplitude of the external clock also?

    If that is the case, then how it work in my case - amplitude 2V(square wave varying from 0V to 2V).

    Also I found that the altering the amplitude/offset of the external clock have a impact on the DOUT amplitude also. 

    Please let me know your thoughts on the above scenario.

    Thanks and Regards,

    Makesh

  • 0 in reply to MAKESH KANNAA P G
    TI__Guru** 113765 points
    Hi Makesh,

    How are you applying the external clock? Are you using a function generator? Do you have some scope shots you can show of the clock input to the ADS1218?

    If you are using a function generator, you must make sure that there is no negative (below ground) portion of the input signal. Usually you would need to add a DC offset to make sure the P2P signal is within 0 to 5V. Second, you cannot rely on the function generator to show the correct voltage. The function generator output usually is based on a 50 Ohm load. If DOUT is changing in amplitude, then this sounds as if you are over-driving the input of the clock greater than the supply voltage.

    Best regards,
    Bob B
  • 0 in reply to Bob Benjamin
    Prodigy 80 points

    Hi Bob,

    Thanks for the response!

    The higher amplitude in DOUT signal got fixed after adjusting the external clock to 0V to 5V.

    We have one more query!

    Whenever the last bit of DOUT is high, the signal gets decayed slowly.

    I have attached the captures for your reference.

    -----

    Capture details:-

    We are trying to read the register having value 0Fh.

    Since the last bit of the register is one, the DOUT is getting decayed. But still we could infer the value as one, as the signal at DOUT remains high at the falling edge of the SCLK. 

    Could you please explain the above behavior.

    Our Configuration,

    AVdd = DVdd = 5V. SCLK = 1KHz, Fosc = 2.4576MHz(through function generator), Fmod = 19.2KHz, Fdata = 10Hz.

    Thanks and Regards,

    Makesh

  • 0 in reply to MAKESH KANNAA P G
    TI__Guru** 113765 points

    Hi Makesh,

    This is normal behavior for the ADS1218 in that after the last SCLK the output of DOUT changes to a high impedance state and is no longer driven.  This is indicated in the Timing Specification Table as t9 shown on page 9 of the datasheet. So there is a hold time after the last falling edge of SCLK to make sure the DOUT is read correctly.

    Best regards,

    Bob B