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ADS7223: CID in full clock mode

Lutz Naumann
Expert 6180 points
Part Number: ADS7223
Other Parts Discussed in Thread: ADS8363EVM

Hello Team,

we are using the ADS7223 in full clock mode. Our idea was to read the CID with each conversion for plausibility testing. It seem that in this mode the channel number reported is always "00" when CID = "0" which normally should report the Channel ID as per the description of BIT5 (CID disable) on page 35 of the datasheet. There is a hint above the diagrams on page 27 of the datasheet.

However, is there any way to read the CID when using full clock mode? Or is this feature simply not available in full clock mode?

many thanks

Lutz

  • 0
    TI__Guru 63266 points

    Hi Lutz,

    Thank you for your post.

    Can you check whether the customer is using pseudo- or fully-differential inputs (PDE = 0 or 1)? Also, how is the customer selecting the channel - manually or automatically (M0 = 0 or 1)?

    In Table 4, it looks like Channel Information is only not available when PDE = 1 and M0 = 1.

    Best regards,

  • 0 in reply to Ryan Andrews
    TI__Expert 6180 points

    Hi Ryan, it is pseudo diffetential input mode andnthebchannelsnswlxted manually. We would like to know if switchong the channels has happened.

    Thanks

    Lutz

  • 0 in reply to Lutz Naumann
    TI__Guru 63266 points

    Ok, so PDE = 1 and M0 = 1?

    I'll have to talk with Tom Hendrick about what it could be. I'll get back to you soon.

    Regards,

  • 0 in reply to Ryan Andrews
    TI__Guru 63266 points
    Hi Lutz,

    I'm still looking into what this could be caused by. Just to confirm - which SDOx is the customer using? Are the outputs coming out on the same SDOx or separate SDOA and SDOB?

    Regards,
  • 0 in reply to Ryan Andrews
    TI__Expert 6180 points

    Hi Ryan,

    It is Mode 1 and addressing the next channel manually, Pseudo-Diff on all channels and both SDOx are separate to get the speed up to 1MSPS.

     

    Thanks

     

    Lutz

  • 0 in reply to Lutz Naumann
    TI__Guru 63266 points
    Hi Lutz,

    We are going to try to bring up an EVM in the lab and verify this. I expect that you should see either:

    00 or 10 for ADC A (SDOA)
    01 or 11 for ADC B (SDOB)

    where the MSB corresponds to Channel 0 or 1 and the MSB-1 is fixed for each SDOx.


    Best regards,
  • 0 in reply to Ryan Andrews
    TI__Expert 6180 points

    Thanks Ryan,

    this is what we were expecting as well. Unfortunately in our case the MSBs don't report what channel is being sampled. According to the designer we get 00. We are not sure if we are doing something wrong.

    thanks

    Lutz

  • 0 in reply to Lutz Naumann
    TI__Guru 63266 points

    Hi Lutz,

    Sorry for the delay. We have an ADS8363EVM (same interface) that we are going to bring up in the lab today.

    Meanwhile, can you share a capture of the interface and tell us the clock frequency and data rate?

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    TI__Expert 6180 points

    Hi Ryan,

    the part is operated in full clock mode, Mode I, with 1MSPS per ADC. 12bit plus the 2 CID Bits. I do not have the exact SPI clock frequency. But for the functionality of the CID it should not matter from my understanding As this is more about the content of the frame.

    thanks

  • 0 in reply to Lutz Naumann
    TI__Guru 63266 points

    Hi Lutz,

    Posting a summary of our offline conversation here to close this out:

    1. When using separate SDO pins (A and B), the Channel ID bit corresponding to ADC A or B might be held low and not used. We are still looking to confirm this using differential inputs.
    2. In Pseudo-Differential mode, it’s not possible to indicate all four possible channels with a single bit, so we suspect that the channel ID bits work differently in this mode. Instead of using one bit for Channel 0/1 and the other bit for ADC A/B, it appears that both bits must be used to implement the 2-bit channel counter.
    3. The customer should be able to use the 2-bit channel counter with Mode I by enabling both the CID bit and the CE bit in the CONFIG register. The contents of the CID bits at the beginning of each frame should then cycle between 00, 01, 10, and 11 to indicate each of the four pseudo-differnetial inputs. Separate SDOs must be used to read the data from each ADC.

    Best regards,