ADS7049-Q1: SCLK input timing requirement

Shinya Sawamoto

Part Number: ADS7049-Q1

Hello team,

I have a couple of questions about external SCLK input for ADS7049-Q1.

The tPH(PL)_CK is required 0.45~0.55tSCLK duty cycle in the Timing Requirements.
1) Is this requirement same through all range of the SCLK rate of 0.016~32MHz?
2) What kind of an issue would be expected if the SCLK was exceeded the max 0.55tSCLK?
3) How comes the max 0.55tSCLK requirement is determined?

As a background of these questions is that to keep 0.45~0.55tSCLK on the clock source may be sometimes difficult, so I'd like to know what would happen in that violated case with considering how marginal this device can cover.

Thanks in advance.
Shinya Sawamoto

over 5 years ago

0 Cynthia over 5 years ago

TI__Mastermind 24940 points

Hello,

This timing requirement describes the high and low time of one square clock pulse. It ensures that the clock signal is a flow of equal square shapes, eliminating any arbitrary set of high or low pulses. It is consistent across all clock frequencies.
As the max and min are given in the datasheet, we strongly suggest staying with them as anything outside the limits is not guaranteed. The device could possibly not clock the falling edge of the clock and data can be missed.
Regards, Cynthia

0 Shinya Sawamoto over 5 years ago in reply to Cynthia

TI__Expert 5260 points

Thanks,
I may send you an email when more discussion is needed.

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ADS7049-Q1: SCLK input timing requirement