SM73201-ARC-EV: RD 195 Safety Test Fail

rjb

Part Number: SM73201-ARC-EV

Hello,

I am using RD-195 Arc Fault detection Development. My built configuration is TM320F28033 / 64 pins package. The only change in the code is in the linker file

where I added FLASHA and FLASHC_1 in the end.

After that I successfully complied the program along with new CRCs in the gGoldenCRC for the changed region.

Problem,

My periodic self test fails randomly at one of the flash sectors (viewed it in debug mode). If I run the program again it runs fine for some time then fails again at the same or different flash / ram tests.

Can you please suggest me what might be the problem ? Any inputs will help.

Thanks.

over 6 years ago

0 Ozino Odharo over 6 years ago

TI__Mastermind 20764 points

Rahul,

Are there any other sections of memory assigning information memory regions to the same locations?

Regards,
Ozino

0 rjb over 6 years ago in reply to Ozino Odharo

Intellectual 470 points

Hello Ozino,

Yes Newly assigned sections FLASHA for 6, FLASHC_1 is assigned for 3 and FLASHD_1 for just 1 information portions of the code.

All the other one are assigned to1 to 3 regions.

Thanks,

Rahul

0 Ozino Odharo over 6 years ago in reply to rjb

TI__Mastermind 20764 points

Rahul,

Can you attach a copy of your linker command file? Were there any build errors before adding the addtionial sections of FLASH to the .text field.

Here is a wiki page regarding splitting memory: processors.wiki.ti.com/.../C28x_Compiler_-_Understanding_Linking

Regards,
Ozino

0 rjb over 6 years ago in reply to rjb

Intellectual 470 points

Fullscreen F28033_FLASH_ArcDetection.txt Download

/*
//###########################################################################
//
// FILE:	F28033_FLASH_ArcDetection.cmd
//
// TITLE:	Linker Command File For F28033 Device
//
//###########################################################################
// $TI Release: C2000 DC Arc Detection $
// $Release Date: Apr 27, 2016 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2803x_Headers\cmd
//
// For BIOS applications add:      DSP2803x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP2803x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2803x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2803x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP2803x_headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F28033
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F2803x are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         L0 memory block is mirrored - that is
         it can be accessed in high memory or low memory.
         For simplicity only one instance is used in this
         linker file.

         Contiguous SARAM memory blocks or flash sectors can be
         be combined if required to create a larger memory block.
*/
--diag_suppress 16002

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   PC_TEST_1   : origin = 0x0087FC, length = 0x000004     /* PC test function 1 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
   FLASHH      : origin = 0x3F0000, length = 0x001000     /* on-chip FLASH */
   FLASHG      : origin = 0x3F1000, length = 0x001000     /* on-chip FLASH */
   FLASHF      : origin = 0x3F2000, length = 0x001000     /* on-chip FLASH */
   FLASHE_1    : origin = 0x3F3000, length = 0x000AAA     /* on-chip FLASH */
   PC_TEST_2   : origin = 0x3F3AAA, length = 0x000004     /* on-chip FLASH */
   FLASHE_2    : origin = 0x3F3AAE, length = 0x000552     /* on-chip FLASH */
   FLASHD_1    : origin = 0x3F4000, length = 0x000900     /* on-chip FLASH */
   FLASHC_1    : origin = 0x3F5000, length = 0x000554     /* on-chip FLASH */
   PC_TEST_3   : origin = 0x3F5554, length = 0x000004     /* PC test function 3 */
   FLASHC_2	   : origin = 0x3F5558, length = 0x000AA8     /* on-chip FLASH */
   FLASHA      : origin = 0x3F7000, length = 0x000F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   IQTABLES    : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEBDC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML0       : origin = 0x008000, length = 0x0007FC 
   RAML1L2     : origin = 0x008800, length = 0x000800     /* on-chip RAM block L1,L2 */
   RAML3       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L3 */
   
   /* FLASHB reserved for EEPROM emulation */
   FLASHB      : origin = 0x3F6000, length = 0x001000     /* on-chip FLASH */

   FLASHD_2    : origin = 0x3F4900, length = 0x000700     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/

SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHH,     PAGE = 0
   .pinit              :>> FLASHE_1 ,  PAGE = 0
   .text               :>> FLASHE_1 | FLASHE_2 | FLASHF | FLASHG | FLASHH  ,   PAGE = 0
   codestart           : > BEGIN       PAGE = 0
   ramfuncs            : LOAD = FLASHC_2,
                         RUN = RAMM0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0
                         
   psa_crc             : LOAD = FLASHG | FLASHF,
                         RUN = RAMM0,
                         LOAD_START(_PSA_CRCLoadStart),
                         LOAD_END(_PSA_CRCLoadEnd),
                         RUN_START(_PSA_CRCRunStart),
                         RUN_END(_PSA_CRCRunEnd),
						 LOAD_SIZE(_PSA_CRCLoadSize),
						 PAGE = 0
                         
   pc_test_section_1   : LOAD = FLASHG | FLASHF,
                         RUN = PC_TEST_1,
                         LOAD_START(_PC_Test1LoadStart),
                         LOAD_END(_PC_Test1LoadEnd),
                         RUN_START(_PC_Test1RunStart),
                         RUN_END(_PC_Test1RunEnd),
						 LOAD_SIZE(_PC_Test1LoadSize),
						 PAGE = 0  
						 
   pc_test_section_2   : > PC_TEST_2, PAGE = 0
   pc_test_section_3   : > PC_TEST_3, PAGE = 0
   
   STL_Test_utility    : > RAMM1,    PAGE = 1
   STL_psa_crc_vars    : > RAMM1,    PAGE = 1
   STL_crc_test_data   : > FLASHD_2, PAGE = 1

   STL_CRC_calc		   : > FLASHA, PAGE = 0
   STL_CRC_TABLE       : > FLASHA, PAGE = 0
   
   csmpasswds          : > CSM_PWL_P0  PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : RUN = RAML0,
   						 RUN_START(_StackBottom),
   						 RUN_END(_StackTop),
   						 PAGE = 1

   .ebss               :>> RAMM1 | RAML0,  PAGE = 1
   .esysmem            : > RAMM1,          PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             :>>  FLASHC_1 | FLASHC_2 | FLASHD_1 | FLASHA,    PAGE = 0
   .switch             :>>  FLASHC_1 | FLASHC_2 | FLASHD_1 | FLASHA,    PAGE = 0

   /* Allocate Fixed Point FFT areas: */
   FFTtf			   : > FLASHD_2,  PAGE = 1 
   FFTipcb	 		   : > RAML3, 	  PAGE = 1  
      
  /* Allocate Arc Detection Test Vector areas: */
   ArcTest			   :>>  FLASHA | FLASHC_1 | FLASHC_2,   PAGE = 0

  /* Allocate Raw ADC Capture buffer area: */   
   RawAdcBuffer		   : > RAML1L2,    PAGE = 1
   
   /* Allocate IQ math areas: */
   IQmath              : >  FLASHA,    PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Before adding the flash region this is the error.

After addition of extra regions build was successful. without any errors.

Please find the linker file I have attached herewith.

0 Ozino Odharo over 6 years ago in reply to rjb

TI__Mastermind 20764 points

Rahul,

Can you split the memory for the psa_crc and pc_test_section_1 sections using >>

GIve this a try and let me know if you are still observe the same issues.

Regards,

Ozino

0 rjb over 6 years ago in reply to Ozino Odharo

Intellectual 470 points

Problem in the Safety Test was due to debug mode PSA_CRC calculations.
Removed from the debug mode and worked like charm.

Thanks for your help though, Ozino.

0 Ozino Odharo over 6 years ago in reply to rjb

TI__Mastermind 20764 points

Rahul,

Great to hear that you fixed your issue. Thanks for sharing your findings.

Regards,
Ozino

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SM73201-ARC-EV: RD 195 Safety Test Fail