Hello,
we are using the ADS5292 with 80MHZ ADC input clock. We have enabled the decimation filter with custom coefficients and decimation by 8. When setting the output data rate to 0x0003 (divide by 8), no LCLK is output, we can only see a FCLK. When we set the output data rate to 0x0002 (divide by 4) LCLK is output. We have set all registers according to the data sheet (see code below). Do you have any idea why data rate divide by 8 doesn't work?
_delay_ms(10);
xio_SetOutput(pinAdcResetOut);
_delay_ms(10);
xio_ClrOutput(pinAdcResetOut);
_delay_ms(10);
writeAdcReg(0x46, 0xA215); // 2 wire LVDS output
writeAdcReg(0x24, 0x00aa); // Invert channels 2, 4, 6 and 8
for(U8 i = 0; i < NUMBER_OF_FIR_COEFFS; i++)
{
volatile U16 firCoeffInt;
firCoeffInt = (U16)(firCoeffs[i] * (2 << 10));
writeAdcReg(0x5A+i,firCoeffInt|0x8FFF);
}
writeAdcReg(0x29, 0x0002); // Global Filter an
writeAdcReg(0x2E, 0x0041); // Decimate by 8, custom coefficients
writeAdcReg(0x14, 0x00FF); // Low frequency noise suppresion on
writeAdcReg(0x38, 0x0003); // Output rate is ADC rate/8
Additional question: Is the calculation of the coefficients correct? We use real coefficients and multiply them by 2^11.
Thanks in advance
Marc