ADS1255: DRDY pulse high length

Hi Greg,

The /DRDY will be driven (back to) high either by clocking out all 24-bits of data OR just prior to the next conversion's completion (in the case that data was not read - see Figure 24 in the datasheet).

I would expect for the time between /DRDY falling edges to be the same since this is outside of your control (this will be determined by the ADC's master clock frequency and the programmed data rate), where as you have some control over when the rising edges occur. Note, if you switch ADC channels (or some other input configuration) the digital moving average filter will have to recompute the moving average, and so the first conversion after this will take longer to complete.

You might need to check on an oscilloscope when you are reading data to see if you are not reading every conversion result or if you are not consistently responding to the /DRDY interrupt and reading data soon after the /DRDY falling edge. If you are polling or using a timer to read data, this could also cause the time between rising edges of /DRDY to vary.