I would like clarification on the tCSS and tCSH setup and hold constraints for the CS_n Chip Select signal and the SCLK clock. The Timing Specifications table and the Figure 3 diagram are not totally clear in my interpretation. What's throwing me is the "typical" numbers in the Timing Specifications table. For tCSS for example, I'm given a 10 ns MINIMUM time. I would interpret that to mean that my CS assertion can be no LESS than 10 ns prior to the rising edge of SCLK. But there in the same line of that table is a "typical" tCSS of 4.5 ns, which is LESS than the 10 ns minimum given. Likewise for tCSH I'm given 10 ns minimum, but the "typical" is given as 0.
Please clarify: Is the constraint that the assertion of CS_n be WITHIN the narrow +/- 10 ns window around the SCLK rising edge, or must CS_n be asserted OUTSIDE the +/- 10 ns window around the SCLK rising edge?
There are other cases of the "typical" times not making sense in the Timing Specifications table. tDS has a typical of 3 ns but the minimum is 10 ns. tDH has a typical of 3 ns but the minimum is 10 ns. What exactly are the "typical" times telling me?
Thanks for clarifying!
