• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 339 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1278: Operating with Slower Sample Rate?

Duncan MacGregor
Intellectual 470 points
Part Number: ADS1278

We have an application where we are planning on using the ADS1278 to simultaneously sample 8 channels but only need to sample all the channels at 200 Hz. We plan on using the high-resolution mode which is spec'd at 52k SPS. Is it possible to run at a much lower speed to only run at 200 SPS? What is the part configuration to make this happen?

Appreciate your help.

  • 0
    TI__Mastermind 46860 points
    Hello Duncan,

    You can run the Master Clock (Fclk) as low as 100kHz, and all resulting data rates will scale accordingly.

    For High resolution mode, the data rate, Fdata, is equal to Fclk/512. For an output data rate of 200sps, you can set Fclk=512*200=102.4kHz.

    Specific Pin Configuration:
    Pin 10, CLKDIV high (IOVDD)
    Pin 33, MODE1 low (DGND)
    Pin 34, MODE0 high (IOVDD)
    Pin 27, CLK (102.4kHz referred to IOVDD levels)

    Also note that SCLK (for SPI) cannot exceed the Master Clock rate (SCLK<=102.4kHz).

    Regards,
    Keith N.
    Precision ADC Applications