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ADS1118: Delta-Sigma ADC Sample Timing

J.Schweiger
Expert 1745 points
Part Number: ADS1118

Hello,

I am looking for information regarding timing of input-capture sampling, specifically for the ADS1118. I am using the 860SPS rate and have a single-ended input.

In reference to the SPI transaction to request a conversion, when does the actual sampling take place (e.g., when does the sample need to be stable in reference to SPI request for a conversion)?  Note that from my testing of a fast-changing PWM signal, I find reasonably accurate conversion only if signal is stable from about 250us to 1000us after the SPI transaction to request a conversion.  Although this test result seems reasonable as the ADC is continually sampling during the conversion, I assume that the averaging that takes place is skewing my results and would like to better understand the timing from when SPI transaction requesting conversion takes place until when the sample/averaging is started until when the sample/averaging is completed.

  • 0
    TI__Guru* 98025 points
    Hi,


    I wasn't exactly sure about how to specifically answer this question. However, there are two things that you should be aware of for timing the conversion and how the data is taken after that.

    If you are using single shot conversions, The conversion start occurs after the 16 bits of the configuration register is read in from the SPI. However, if you are in continuous conversion mode this is a little different. If you are running with a particular configuration, and you change the configuration (say from one channel to the next), the start of the conversion with the new configuration does not take place immediately. The device will complete the conversion in progress, and then start a conversion with the new configuration.

    The ADS1118 is basically a delta-sigma (or oversampling converter). This means that there are many input samples taken to make a single output data word. The device is sampling at the modulator rate and digitally filtered to get the respective output data rates. In this device the modulator rate is 250kHz. For the default data rate of 128SPS, the modulator samples the input almost 2000x for a single output data. The resulting effect is that the output data looks like a time average of the input during the entire data period.

    Hopefully this covers your question. If it doesn't, post back and we'll discuss it more.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Expert 1745 points
    Thank you Joseph. I appreciate your response and clarity around difference between modes; I am using single-shot conversions in my application.

    To clarify my question, is there any significant processing time for the ADC after the SPI transaction is complete until the data ready signal is given? Based on your explanation, it sounds like for single-shot conversions there is no significant delays and the signal is continuously averaged the entire time between when the SPI transaction completes until the data ready signal is given. Is this correct?
  • 0 in reply to J.Schweiger
    TI__Guru* 98025 points
    Hi,


    That is basically correct. There may be a 20us delay to start up the device, and there may be a handful of modulator clocks after collecting the ADC input sampling to accumulate the output data. However, for the great majority of the data period, the ADC is sampling the input at the modulator clock frequency.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Expert 1745 points
    Got it. Thanks for your quick and thorough responses Joseph!