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ADS127L01: synchronized data acquisition of multiple vibration sensors

user5922017
Prodigy 90 points
Part Number: ADS127L01
Other Parts Discussed in Thread: THS4551
Hi,
We are using ADS127L01 for vibration sensor data acquisition, like proximeter, accelerometer and velocity sensors. the sampling rate is fixed at 128KHz. Here are a few questions. 
1. The sensor is a differential input. the input range is + REF ~ - REF, or the voltage difference between AINP and AIN. There might be situations when an operator reversed the positive/negative wire in the field, causing a negative voltage. What should we do in this case?  Does the voltage still need to be high than GND?
2. If the sampling frequency is fixed at 128kSPS, and power consumption is not a concern, is VLP mode is the best of HR, LP, and VLP?
3. What is the order of the Wideband 1 (0.45~0.55) FIR filter? is it a Butterworth filter? 
4. The cut-off frequency of the analog anti-aliasing filter is Fmod/2, about 2MHz. In the datasheet, the recommended design THS4551,  the discrete low-pass RC combined with the active MFB filter, the result is a third-order anti-aliasing filter, The cut-off frequency is about 100KHz. is this necessary?
5. If we choose a fixed 128kHz Sampling frequency, would it be best we put an anti-aliasing filter at 64kHz before the data converter?
5. Can START signal be used as the synchronous signal of multiple ADS127L01? The main control FPGA can be linked through the GPIO port.

6. The setting of CRC bits can be set only by writing registers. Can it be saved after a power failure, without re-setting the CRC?
Thank you
  • 0
    TI__Mastermind 46200 points
    Hello,

    Welcome to TI's E2E Community.

    Answers to your questions.
    1. The voltage on each of the input pins, AINP, AINN, must always be between AGND and AVDD for normal operation, and ABS max of AGND-0.3V and AVDD+0.3V. In the case of AVDD=3.0V, the input range must be between -0.3V and 3.3V worst case. Assuming Vref=2.5V, AINN=0V and AINP=+2.5V for positive full scale, and AINN=+2.5V and AINP=0V for negative full scale. If possible, please send a drawing or schematic showing how you have the ADS127L01 connected to your sensor and I can make further suggestions.
    2. If power consumption is not a concern, and you want best performance (highest SNR), then High-resolution (HR) mode will be best performance. For 128ksps and Wideband filter 2, (HR) mode SNR=110.9dB, (LP) mode SNR=108.1dB, and (VLP) mode SNR=104.9dB.
    3. Wideband 1 filter is different from a Butterworth filter. A Butterworth filter will not have any ripple in the pass band; the Wideband 1 filter has a very small amount of ripple as shown in Figure 74 of the datasheet. Wideband 1 filter is based upon an FIR architecture where the output depends on the current sample and a fixed number of previous samples. This results in a linear phase filter response. If you tried to approximate the Wideband 1 filter with a high order Butterworth, the equivalent order would be over 100.
    4. The digital filter will provide about -116dB of attenuation of signals between Fdata/2 and Fmod. At frequencies near Fmod, there will be very little attenuation provided by the digital filter. The reason for an analog anti-aliasing filter at 100kHz is to make sure at Fmod, you are still getting close to -100dB of attenuation at frequencies near Fmod. Take a look at Figure 112 in the datasheet for a better description. If you used a single order filter with a cutoff frequency of Fmod/2, you will only have about -7dB of attenuation at Fmod. If you know that your sensors cannot have any significant signal magnitude near Fmod (16.384MHz), then maybe a single order anti-alias filter will work. It depends upon the rest of your system and the out-of-band signals you expect to be present.
    5. For a fixed 128Ksps output data rate, placing an anti-alias filter at 100kHz is a good compromise. Placing the cutoff frequency closer to 64KHz will attenuate your signals in the passband more. At 100kHz, a third order low pass filter will provide adequate attenuation at Fmod.
    6. YES, START can be used to synchronize multiple ADS127L01 devices running from the same Fclk.
    7. Any register modified will return to its RESET value after a power-cycle. Note that by default, CRC-4 is enabled on power-up/reset. If this is acceptable, then you would not need to update this register setting after a power cycle.

    Regards,
    Keith N.

    Precision ADC Applications