Part Number: TSW14J56EVM
Hello,
My team is using a TSW14J56EVM mated with an ADC12J4000EVM. Currently, the ADC is configured in bypass mode with K=4 with a DEVCLK of 1.6 GHz, which gives a SYSREF of 10 MHz. At the moment, we are working with your team on a firmware solution to bring the SYSREF signal out on an SMA connector on the capture board that we could use to synchronize the LMFC to another device (original forum post here).
We have determined that it may also be convenient to lower the SYSREF frequency from 10 MHz to 2.5 MHz since the other device has a convenient SYNC port whose input must be <9.1 MHz. In order to do this, I believe that we must change the SYSREF divide settings on the LMK04828 (in register 0x13A and 0x13B) and change the K value from 4 to 16 (since SYSREF=1.6e9/(K*F*5) per the datasheet) both on the FPGA and ADC. While changing the K value on the ADC is fairly straightforward using the GUI, I'm confused about what the K value should be set to on the FPGA. When I open up the dynamic configuration window in HSDC Pro to modify the JESD IP Core parameters, I find that each of the parameters differs from what they should be set to according to Table 11 of the ADC12J4000 datasheet. Additionally, even while K=4 on the ADC, the dynamic configuration window lists K=32.
Would you be able to let us know if A. setting the SYSREF to 2.5 MHz would be possible and B. how we should go about configuring the ADC board and the FPGA to accomplish this?
Thank you for your help!
-Russell
