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ADS1120: Single-ended input linear range / schematic check

Christopher Shields
Prodigy 40 points
Part Number: ADS1120

Hello all,

I'm planning on testing the ADS1120 in an instrument system I'm working on.

The input is from one draw-wire sensor which has a single ended, unipolar DC output of 0 to 10V. The input should not fluctuate more than one mV per day.

I am planning on using a 5V VDD and using a voltage divider on the input signal to get 0-5V for maximum SNR. I plan on setting the voltage reference to VDD and disabling the PGA.

There are details about the linear range for the PGA inputs in the datasheet - does this apply for the inputs regardless of the PGA being enabled? E.g., should I expect a usable range of 0.2V to 4.8V?

Any comments appreciated, including the implementation of the anti-aliasing/input LPF.

Many thanks,

Chris

  • 0
    TI__Guru** 113765 points
    Hi Chris,

    Welcome to the E2E forum! The sensor input should work as you have it, but I do have a couple of comments. But before I comment I should answer your direct question first. With the PGA disabled (bypassed) you are not restricted to the same input range as with it enabled. See section 6.3 of the ADS1120 datasheet on page 6. Note that in the ANALOG INPUTS section the Absolute input voltage range is the same as the Common-mode input voltage range when the PGA is disabled. This means a valid measurement is possible with inputs as low as AVSS-0.1V and as high as AVDD+0.1V. In the end you are not restricted to the same input range with PGA disabled as with PGA enabled and will have a usable range from 0 to (AVDD-AVSS). See section 8.3.2.2 on page 24 for more information on Bypassing the PGA.

    With all that said, the input range will correspond with the reference range excluding any offset or gain error. Offset and gain error can push the measurement away from the ideal measurement range. The typical gain error is +/- 0.015% which could be a factor if your measurement is near +full-scale. Also, if your analog supply is noisy or not stable you will see additional error as the supply is being used as the reference.

    As to the comments, the calculation for fc I have at 1.35kHz. This is sufficient for antialiasing.

    You show a TVS diode that will have a specific clamp voltage. Most likely this clamp voltage will be much higher than 10V. The voltage divider will place AIN0 greater than AVDD+0.3V (from Absolute Maximum Ratings) when the input voltage is greater than 10.6V. This current through AIN0 must be limited to no more than 10mA. Depending on the clamp voltage, you may need to size the resistors accordingly so as to limit the current into AIN0.

    One other comment regarding the voltage divider. Resistors can drift which can cause a measurement error. Usually precision resistors are also low drift.

    Best regards,
    Bob B
  • 0 in reply to Bob Benjamin
    Prodigy 40 points
    Hi Bob,
    Many thanks for the excellent insights. I'm a lot more confident now about how to approach this.
    Good tip about the TVS clamp voltage - I'll look into it.
    Thanks and best regards,
    Chris