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In general, the SCLK frequency you need will depend on the numbers of ADC channels, the number of bits per channel, and the data rate. Each device will have unique requirements depending on the mode of operation.
Check out the steps below, I'll use the ADS1298 for this example:
The ADS1298 has two modes for reading data: RDATAC Mode (read data continuously) and RDATA Mode. In RDATAC Mode, the device's output shift register is updated with new data from all channels after each conversion automatically. The completion of a conversion is indicated by the falling edge of /DRDY. All data must be read before the next /DRDY falling edge. Otherwise, it will be overwritten and lost.
In RDATAC Mode, the maximum SCLK period (minimum SCLK frequency) can be calculated as:
where "4*tCLK" accounts for interface delays and "+ 24" accounts for the 24-bit STATUS word at the beginning of each transaction. For an ADS119x device, the number of bits per channel changes to 16 and the STATUS word remains as 24 bits.
In RDATA Mode, the output shift register is loaded with the most recent conversion data "on-demand." Therefore, there is no restriction on the minumum SCLK frequency for this mode. The user may miss samples if the data is read too slowly, but the current data will not be overwritten or corrupted by the next conversion.
The maximum SCLK frequency depends on the applied DVDD voltage. For DVDD between 2.7 V and 3.6 V, the fastest SCLK you can use is 20 MHz (50-ns period). For a DVDD less than 2.7 V, SCLK is limited to a period of 66.6 ns or approximately 15 MHz. Always refer to the Timing Characteristics table in the datasheet for your specific device.
FIGURE 1: Minimum SCLK Frequency for ADS1298
This post applies to ADS1191, ADS1192, ADS1291, ADS1292, ADS1292R, ADS1294, ADS1294R, ADS1296, ADS1296R, ADS1298, ADS1298R, ADS1299-4, ADS1299-6, and ADS1299.
