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DDC114: Questions on Implementation

Mitchell
Expert 4915 points
Part Number: DDC114


Hi Team,

My customer is using the DDC114 and has some questions I'd like your feedback on.

The first is around the differential signals for the serial interface of the chip: DCLK, /DCLK, DOUT, /DOUT. If we have a solid ground, how important is the differential signaling regarding noise coupling? I know that's a loaded question, but is it recommended as best practices in general or is it to address long data bus traces or converters at the end of cables? 

Second, we have generated a clock for the DDC by cheating in the past taking our resonator sine wave into a logic buffer chip to convert to a square wave. We don't like this because the resonator and oscillator have a longer signal trace to drive, as well as probably more jitter due to this configuration. So they have opted in a new revision to use a small MEMS 4MHZ oscillator right next to the DDC and then use a flip flop to synchronize the serial data clock with the local oscillator. In the datasheet it mentions for best performance to use the main MCU system clock to also drive the DDC, but I have a feeling the previous setup converting the sine to a square pulse train is not anywhere near an ideal system clock. So, I'd like to hear your thoughts on this.

Thanks,
Mitchell

  • 0
    TI__Genius 12025 points
    Hi Mitchell,

    How are you?
    Thank you for helping customer use DDC114 device.
    I would ask the customer's questions to our system engineer here,
    will reply to you about 2 days.

    Thank you!
    And best regards,
    Chen
  • 0 in reply to Chen Kung
    TI__Genius 12025 points

    Hi Mitchell,

    How are you?

    For the customer's first question about the differential pins:

    DCLK, nDCLK, DOUT, nDOUT, DIN, nDIN

    as the DDC114 data sheet page13 mentioned

    these complementary signals are designed to help reduce

    the digital coupling.

    (Note: that means if we don't use those complementary signals

    then the digital "noise" must go through DGND instead of its differential pin.

    Then when the heavy "noise" working on the DGND, it might be very easy

    to couple to the AGND and also will affect the analog inputs.)

    Also another concern for the differential signal traces layout is

    every differential pair traces such as used for long bus or cable.

    The other question is for your input clock.

    Please ensure the master clock CLK is synchronized with CONV and DCLK (nDCLK)

    and make sure the clock signals avoid overshoot or ringing (according to the data sheet mentioned).

    Clock jitter may not be an issue since A/D Converter starts to work when the integrator has been

    settled down and becomes a DC signal.

    Thank you!

    Best regards,

    Chen

  • 0 in reply to Chen Kung
    TI__Expert 4915 points
    Hi Chen,

    Thank you!

    Just a couple more follow up questions:

    1. What would be a suggested frequency stability for the 4MHZ oscillator that is driving the DDC14 CLK? Is 25PPM sufficient?

    2. In the Complimentary signals section on page 13, we assume the datasheet is looking for a proper differential signalling chip, not just a logic inverter correct? Figure 21 shows a simple logic inverter / buffer to generate the inverted signal. Are there any specific devices recommended here?

    Thanks,
    Mitchell
  • 0 in reply to Mitchell
    TI__Genius 12025 points
    Hi Mitchell,

    Thank you for helping the customer again.
    For the question 1:
    Yes, +/-25PPM is ok. However, is it correct that the customer wants to use MCU
    system (similar to FPGA) to connect input/output signals
    to DDC114 device, right?
    If correct, can we suggest by using 80MHz osc with +/-25PPM (for example, this cost could be almost the same as 4MHz with same PPM's cost)
    and then in MCU system by dividing it down by 20 to generate 4MHz to DDC114's
    input CLK? If possible, it could reduce the PPM as well.
    For the question 2:
    That data sheet figure 21 showed is not good for analog signals
    only used for digital signals such as DIN, nDIN, DOUT, nDOUT only.
    Because between the data clock input and inverted data clock have some
    time delay and will be limited to the low frequency clock speed as well.
    Therefore, we suggest the customer uses the DCLK and nDCLK coming from
    their MCU system output pins to create both signals for DDC114.

    Thank you very much!

    Best regards,
    Chen