Other Parts Discussed in Thread: DAC38RF89
hi,
We have four DACs that we want to operate them at 2500MSPS input data rate and interpolation 2 (using DAC38RF89), or 3333MSPS input data rate and interpolation 2 (using DAC38RF82).
We need to use each of the four DACs we have in our board, to output one analog I-channel and one Q-channel (no modulation inside DAC so NCOs unused). From what I understand, this means that we are confined to the “real input” rows of “Table 9” of “SLASEA6B –FEBRUARY 2017–REVISED AUGUST 2017” datasheet. Thus if we want to utilize 4 JESD lanes for each DAC IC, we have no “official” available modes to work with, i.e. the device does not support such a setup. Am I correct?
The alternative we are thinking, is to keep 8MSbits per TX (MSByte), use mode 82121 with 2TX, leave out lanes RX1, RX3, RX5, RX7 and disable the unconnected lanes from register JESD_LN_EN. Should we expect any problems with the interface using this approach?
Is there any other way you can suggest for using 4 JESD lanes per DAC?
thanks a lot in advance
KR
Vincenzo