ADC12DJ3200: Maximize SFDR at 1333.333 MHz sampling

Hi Forrest
I will try to set up similar sampling conditions tomorrow and see how the results compare to yours.
I'll let you know what I get.
Best regards,
Jim B

Hi Forest

Here is my capture using the ADC12DJ3200EVM with on-board clocking at 1250 MHz and an input signal at 997.77MHz.

I have Foreground and Foreground Offset calibration enabled.

I am notching the interleave offset related spur at Fs/2, but all other spurs are shown and quantified in the performance metrics.

Next is the same signal case, but with Background and Background Offset calibration also enabled.

In this calibration mode the SFDR varies somewhat depending on which ADC cores are active. I did the screen shot of the low-end of the SFDR range in this mode.

In both cases SFDR is limited by HD2 performance. I haven't seen an excessively high HD3.

Can you export the ADC register settings so I can compare them to what I have in these measurements? If possible the order in which the ADC registers are programmed would also be useful, but the basic settings will be useful as well.

Best regards,

Jim B

Hi Forrest

Please try this slightly revised sequence/setup. The changes are highlighted in Red.

Clearing ADC RESET pins
spi_write: ADC addr 0 data 0xb0 Configuration A Register CONFIG_A soft_reset ascending addresses 4-wire SPI mode

spi_write: ADC addr 0x2a data 0x2 Clock Control 1 CLK_CTRL1 use LVPECL for sysref. 

spi_write: ADC addr 0x3b data 0x2 TMSTP +/- Control TMSTP_CTRL use LVPECL for tmstp

This step is not needed and provides no benefit if SYSREF calibration is being used later in the sequence.
//spi_write: ADC addr 0x2b7 data 0x1 DEVCLK Aperture Del TAD devclk aperture delay tad_fine = 1

spi_write: ADC addr 0x29 data 0x20 Clock Control 0 CLK_CTRL0 enable sysref receiver
spi_write: ADC addr 0x29 data 0x60 Clock Control 0 CLK_CTRL0 enable sysref processor
spi_write: ADC addr 0x200 data 0 JESD204B Enable JESD_EN disable JESD
spi_write: ADC addr 0x61 data 0 Calibration Enable CAL_EN hold calibration in reset
spi_write: ADC addr 0x2b1 data 0xf SYSREF Cal Config SRC_CFG 256 averages 256 cycles per accumulation
spi_write: ADC addr 0x2b0 data 0x1 SYSREF Cal Enable SRC_EN starts SYSREF calibration
ADC0 SYSREF Calibration Done
ADC1 SYSREF Calibration Done
spi_write: ADC addr 0x201 data 0x2 JESD204B Mode JMODE JESD Mode = 2
spi_write: ADC addr 0x202 data 0xf JESD204B K Parameter KM1 K = 16
spi_write: ADC addr 0x204 data 0x3 JESD204B Control JCTRL 2's complement enable scrambler
spi_write: ADC addr 0x61 data 0x1 Calibration Enable CAL_EN enable calibrations
spi_write: ADC addr 0x200 data 0x1 JESD204B Enable JESD_EN enable JESD
spi_write: ADC addr 0x30 data 0xff INA Full Scale Range FS_RANGE_A set chan A to 1000 mVpp
spi_write: ADC addr 0x31 data 0xff ditto…
spi_write: ADC addr 0x32 data 0xff INB Full Scale Range FS_RANGE_B set chan B to 1000 mVpp
spi_write: ADC addr 0x33 data 0xff ditto…

spi_write: ADC addr 0x6C data 0x0 Calibration Soft Trigger Clear

spi_write: ADC addr 0x6C data 0x1 Calibration Soft Trigger Set to initiate Foreground calibration after changing FS Range

spi_write: ADC addr 0x48 data 0 Serializer Preemph SER_PE set pre-emphasis = 0

spi_write: ADC addr 0x29 data 0x20 Clock Control 0 CLK_CTRL0 disable SYSREF processing, keep receiver enabled

I think these changes should give some improvement. Let me know what you find.

Best regards,

Jim B

Hi Forrest

Regarding your latest questions:

1) Documentation for the adc12dj3200 states to never write to certain registers (i.e. OADJ_C_INA/B) during an FG or BG cal. If a write to this register is made during BG Cal, are the effects permanent, or could simply running another calibration, FG or BG, resolve the issue? We suspect our original issue with a high 3rd order harmonic was created during one of these register writes. Does this sound plausible?

The effect of the writes won't necessarily be permanent. Running a new Foreground Offset or Background Offset calibration would restore those values you mention.

2) Is there any specific event (or series of register writes) that might cause the 3rd order harmonic to significantly increase when input is simply a tone? This has been seen on our evaluation board but a FG Cal quickly eliminates the issue and brings the harmonics back down.

Changing CAL_SOFT_TRIG from 1 to 0 prepares the calibration block to start a new calibration. In this state large harmonic distortion will be seen. Setting this bit back to 1 re-starts the calibration block and restores performance.

3) What is the algorithm for FG or BG cal? For example, what values is it measuring and adjusting? Can we see certain registers change or is there even access to these cal values?

The algorithm is proprietary. The results of the calibration can be read-out and stored, and written back into the device for future use. This is discussed in the CAL_DATA_EN and CAL_DATA register descriptions. The calibration settings are not intended to be decoded or adjusted by the users.

4) If running with FG Cal, at what temperature deltas should FG Cal be re-run? At what other point would a FG Cal need to be re-run?

See Figures 11-15. These show performance versus temperature in FG calibration mode with calibration at each temperature point versus calibration only at 25C ambient temperature. Based on your system requirements you can decide how much performance degradation is tolerable and then determine the delta-T where re-calibration should be performed.

5) When does the converter initiate a BG Cal?

With BG Calibration enabled the ADC cores are in a continuous process of being re-calibrated and swapped. The entire process to calibrate all cores takes less than a second.

Low Power BG Calibration mode adds programmable waiting periods into the process to reduce the average power consumed. Please refer to 7.4.6.2 Low Power Background Calibration (LPBG) Mode for more details.

I hope this is helpful.

Best regards,

Jim B