Deserializer - Frame grabber for LVDS & 4K LVDS video signals

Hello Davide,

for these three setup you can use only one Deserializer; DS90UB948 for example.
Note: Signal_1 has a high resolution, hence you will need to use dual lane mode between SER and DES to support this resolution.

You can buy the EVM from here: www.ti.com/.../ds90ub948-q1evm
This Deserializer have oLDI (LVDS) output interface, so you need to make sure this is the correct interface for your application.

I did not mean that you need to use another Serializer, but you need to use your Serializer and the Deserializer in Dual lane mode to support the higher resolution.

Hello,
In your applications
lets assume 10% overhead for blanking
PCLK = Vert * Horiz * (1 + Blanking%/100) * Refresh Rate

Signal_1 DS90UB949 2800x960 – 4K LVDS 30, PClk Est - 88.704e6, Single or Dual FPD

Signal_2 DS90UB947Q1 1200x1920 LVDS 30, PClk Est - 76.032e6 - Suggest Single FPD

Signal_3 DS90UB947Q1 1240x225 LVDS 30, PClk Est - 9.207e6, (this is below the min rate of 25Mhz) Single FPD
increase to higher refresh, and larger blanking time to get >25Mhz PClk

In all 3 cases, you could couple this to a DS90UB928 or DS90UB948 deserializer. You can wire the 2nd FPD Link for future expansion.
You would then use an DVI Mux, or convert the LVDS signals 947 to HDMI 949 signals.

The OLDI (4 data 1/7 clk)LVDS or HDMI(TMDS 3 data 1/10 clk) LVDS could be multiplexed into a special video card that has a Frame Grabber.
You might just use 3 Frame grabber video cards.

An alternate approach for the deserializer is to use the DS90UB940, so you would capture CSI-2 serdes, instead of video signals. You would still need 3 Deserializers.

Regards,
Joe Quintal

Hello,

There are several specific limits for the Deserializer, each FPD transmission is one Pixel time.

There is a Pixel output clock limit of Single FPD3 - Single OLDI, 96Mhz PCLK

There is a Pixel output clock limit of Dual FPD3 - Dual OLDI, 192Mhz PCLK

Based on 35bit-serialized data, (35 * 96Mhz) =  3.36Gbps FPD line rate.

You need to make sure the output panel or resolution you desire is supported for test by the pattern generator for both active and total display size.

2800 x 960 x 30 x (blanking overhead) < selected FPD3 limit above.

The size listed 2048 x  1080 x 60 x (blanking overhead 10%) =  145.98144Mhz PCLK - still works in Dual OLD mode.

If you want to pretest your design before making a board, I suggest you get a serializer and deserializer EVM, so you can have confidence.

The 947 serializer in Dual OLDI mode has special errata work arounds, PDB must be connected to external GPIO control (not RC), special software overrides.

I will ask the other IVI specialist engineer, to see if there are more constraints, but I think it should work.

Note: as you have a higher data rate, the layout quality, and jitter may limit performance also.

Regards,

Joe Quintal