Part Number: DAC37J82EVM
Other Parts Discussed in Thread: LMK04828
Hello, I running into an issue with the DAC37J82EVM in which the DAC is attempting to establish a JESD link on the falling edge of SYSREF. My current understanding of the JESD protocol is that converters and processors should respond to the rising edge of SYSREF, but that doesn't appear to be how my setup is behaving.
My configuration is the same as it is in this question : e2e.ti.com/.../772847
To reiterate :
- DAC37J82EVM board
- Xilinx VCU118 Demo board
- JESD204 v7.2.1 IP is instantiated
- JESD204B subclass 1
- LMFKS = 4, 2, 1, 30, 1
- 1 GSPS sampling rate, 250 MHz core clock, 10 Gbps line rate
After configuring the EVM and the FPGA, I trigger SYSREF and I observe this on the FPGA :
[1] : Code Group Synchronization
[2] : SYSREF Rising Edge
[3] : Initial Lane Alignment Sequence
[4] : User Data
Since the SYNCB pin from the DAC is already high, the FPGA goes through the link establishment steps and begins transmitting its digital waveform. Note however that the DAC does not output any RF at this point
When SYSREF returns to 0 I observe this :
[1] : SYSREF Falling Edge
[2] : SYNCB request from DAC
[3] : Code Group Synchronization
[4] : ILA Sequence
[5] : User Data
After the falling edge of SYSREF, the DAC requests link establishment via the SYNCB pin and the FPGA go through the link establishment steps again. The DAC also outputs the expected RF waveform from the FPGA at this point. Our system requires all ADCs, DACs and processors to synchronize simultaneously, i.e. on the same SYSREF edge. I've also tried to configure the LMK04828 to invert the SYSREF signal going to the DAC, but as far as I can tell when probing with an o-scope that feature doesn't actually change the SYSREF signal in any way.
Is this expected behavior for the DAC? is there anyway to change it?
Thank you,
-Branden
