ADS1672: Delay of DRDY of ADS1672

Masami Michino

Part Number: ADS1672

Dear, All

Customers are using the ADS1672.
Multiple ADS1672 are used but simultaneous sampling is necessary.
For this reason, I have the following questions.
Furthermore, they use the mode of "SCLK_SEL = 1".

a. Under the following conditions, can each ADS1672 be guaranteed to sample on the same CLK edge?
- Connect the same CLK to the CLK terminal of each ADS1672.
- Enter the START signal by observing the specified value of "Figure 3. START Timing".

b. They want to know the CLK edge that output DRDY to see if the ADS1672 was sampled on the same CLK edge.
Therefore, I want to know the Max value of the DELAY value from CLK to DRDY.
Please tell me the Max value of Tclkdr. If it can not be guaranteed, the assumed value (design value etc) is also good.

The questions in b. are necessary to determine the maximum frequency of the CLK they can use.

Please tell me these two.

Thanks, Masami M.

over 6 years ago

0 Keith Nicholas over 6 years ago

TI__Mastermind 46880 points

Hello Masami,

For question (a),YES, as long as both ADS1672's share the same CLK and START signals, they will be synchronized to the same clock edge when following the timing requirements in Figure 3 of the datasheet.

For question (b), as you noted, there is some variation from part to part (Tclkdr) from the falling edge of CLK to the rising edge of DRDY. We do not have any characterization data for the min/max, but you can expect this delay to be 37nS +/-20% over temperature.

SCLK can be at least 2x the speed of CLK. If you monitor a single DRDY output and wait an additional ~15nS, you can assume all DRDY's have toggled and then retrieve data from all ADC's at that time.

Regards,
Keith N.
Precision ADC Applications

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ADS1672: Delay of DRDY of ADS1672