Part Number: ADC128S102
Hi
In the process of testing the ADC128S102, I would like to verify the datasheet specification of the conversion time test(13 clk cycles).
Can you please help me with the test procedure for conversion time test.
Thanks,
Sunitha
Hello,
The device needs a total of 16 sclk cycle to complete one conversion cycle. This conversion cycle is made up of two phases, the acquisition (track) phase and the conversion (hold) phase. The acq phase is a max of 3 clock cycles, and the conversion is 13 clock cycles.
Depending on your desired sampling rate, this will determine the clock frequency used. Say, the max sampling rate of 1 MSPS. This means that the max clock frequency will need to be used of 16Mhz.
These are related as such:
Sampling rate: 1MSPS=1MHz; in seconds this is 1/1MHz = 1us per sample.
The means that in 1 sample, that last 1us, the device needs 16 clock cycles. Thus
Clock period = 1us / 16 = 62.5ns, in hertz this is 1/62.5ns = 16MHz ( the clock frequency)
The conversion phase then would be 13 clock pulses (periods) = 13 * 62.5ns = .813 us
The acquisition phase then would be 3 clock pulses (periods) = 3* 62.5ns =0.188 us
You can check if this equals out by adding them and matching it with the expected sampling rate
0.813us + 0.188us = 1us
Hope this helps.
Cynthia
