Part Number: ADS8668
Hello all,
On page 39 of the datasheet for ADS8668 (12-bit, eight-plus-one analog inputs, SAR ADC), under section 8.4.1.3.1 and as illustrated by Figure 93, is the description of daisy-chaining the device. It is described that the first 16 clocks of an access cycle are for shifting into all of the chained devices a common control/programming word and that the following clocks are for shifting out conversion data from the chained devices, requiring 16 clocks for each device’s data to appear in succession on the SDO line coming out of the last device in the chain. So that a chain of three devices would be accessible with a cycle of 16 + 3 x 16 = 64 clocks total.
Yet, on page 56 of the datasheet, Table 13 under section 8.5.2.3.2 describes various SDO formats, controlled by a 3-bit field of the Feature-Select Register of the device (address 0x03 in the device’s register map), all of which imply that it takes 25 clocks to output a conversion result, followed by nine additional bits of pertinent information.
How are these two functionalities reconciled? If it takes 25 clocks to place on the SDO everything relevant to a sample conversion, how can a daisy chain need only 16 bits per device to output data? Is there a mode for 25-bits output that is incompatible with daisy-chaining? Are there templates that I could look into, regarding the above discussed functionalities?
Best regards
