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TSW1400EVM: error when trying to compile the code for ADS5294EVM

Ramakrishna Bachimanchi
Intellectual 300 points

Part Number: TSW1400EVM

Hello,

I am trying to use ADS5294EVM with TSW1400EVM and I am running into a weird issue. I have the Quartus project file from TI and it compiles good. What I tried doing was convert to vhdl and simplify the code little bit. All the PLL and serdes were set up exactly the same way as the TI's firmware. DCLK(data clock) from the ADC board goes into pins AA7 and AA6 and this one drives a PLL and the output clock of the PLL (2*DCLK) drives the serdes input. When I try to compile the code I get the following error

    Error (176562): Can't place Left/Right PLL "pll_adc_data_acq:inst24|altpll0:adc_pll_config|altpll:altpll_component|altpll0_altpll2:auto_generated|pll1" in PLL location PLL_B1 because the location does not accept Left/Right PLLs

    Error (176563): Can't place Left/Right PLL "pll_adc_data_acq:inst24|altpll0:adc_pll_config|altpll:altpll_component|altpll0_altpll2:auto_generated|pll1" in PLL location PLL_L2 because PLL has a location assignment that is incompatible with the PLL location in the device

    Error (176161): Can't place input clock pin clk_lvds_rx0_p driving fast PLL pll_adc_data_acq:inst24|altpll0:adc_pll_config|altpll:altpll_component|altpll0_altpll2:auto_generated|pll1 in non-compensated I/O location AA7 -- fast PLL drives at least one non-DPA-mode SERDES
    Error (176562): Can't place Left/Right PLL "pll_adc_data_acq:inst24|altpll0:adc_pll_config|altpll:altpll_component|altpll0_altpll2:auto_generated|pll1" in PLL location PLL_T1 because the location does not accept Left/Right PLLs

not sure why am I running into this issue, as I am using exactly the same thing as the TI's firmware. Can someone from the firmware team look into it and please let me know, if I need to add anything to the constraints somewhere, so that it won't give an error with the compilation.

Thanks in advance

Regards,

Ramakrishna

  • 0
    TI__Expert 4880 points
    Hey Ramakrishna,

    I forwarded your question to a device expert. He will get back to you shortly.

    Thanks

    Yusuf
  • 0 in reply to Yusuf%20Agoro
    TI__Genius 12025 points
    Hey Ramakrishna,

    How are you?
    Thanks for using ADS5294EVM with TSW1400EVM.
    Here is how we are using both hardware (EVMs) and software (GUIs)
    shown on the TI ADS5294 Users Guide website:
    www.ti.com/.../ads5294evm
    Please copy User Guide (for more clear detail description) and Software
    (from this website including:
    High Speed Data Converter Pro GUI Installer, v5.00 (Rev. U)
    and
    ADS5294EVM GUI Installer )
    Notice: both programs may need to be used using Windows 7 on your PC
    in order to avoid the installation problem happened.

    Thank you and best regards,
    Chen
  • 0 in reply to Chen Kung
    TI__Guru* 91947 points

    Chen,

    We checked the errors but couldn’t identify the issue causing it. Can you send your modified source code?

     

    We believe the errors must be due to some mismatch in the connection between PLL & SERDES IP during the modification.

     

    Following are the points to note and the way PLL and SERDES IP has to be connected. Please verify this is what you have done.

     

    1.       Following are the PLLs available & Global clock (GCLK) networks in Stratix IV devices and the FPGA part available in TSW1400 has 4 PLLs- B1, T1, L2 and R2

     


     

    2.       We have two PLL instances in design- ipll_top_inst0 and ipll_top_inst1 and 3 SERDES IP instances - ilvds0_insta, ilvds0_instb and ilvds1_inst.

     

    3.       PLL ‘ipll_top_inst0’ should take clock from LVDS pins AA7/AA6 (P/N) and its output should be connected to SERDES IP instance ilvds0_insta and ilvds0_instb. This IP in turn receives data from the LVDS pins of right side banks- Bank6 and Bank5.

     

    4.       PLL ‘ipll_top_inst1’ takes clock from LVDS pins AA28/AA29 (P/N) and its output is connected to SERDES IP instance ilvds1_inst. This IP in turn receives data from the LVDS pins of left side banks- Bank2 and Bank1.

     

    Please ensure PLL->SERDES IP->LVDS pin connections are correct as per below table

     

     

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 300 points

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/73/Laser_5F00_Drive_5F00_Upgrade_5F00_ADC.7zHi Jim,

    thanks for your reply. I followed the example code and modified it based on my needs. I am attaching the code here. Please let me know, if you need more information

    Thanks,

    Ramakrishna

  • 0 in reply to Ramakrishna Bachimanchi
    TI__Guru* 91947 points

    Ramakrishna,

    Did your modifications violate any of the settings per the last post?

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 300 points
    Hi Jim,
    as far as I know, i did exactly the same as the TI example. all the lvds pins I am using are from banks 5 A and 5 C and the corresponding clock is the one that is on the pincs AA7 and AA6
    If I have only altpll, everything compiles fine. Once I add altlvds_tx, it gives me the error about pll being driven by an uncompensated I/O, because it is driving a non-DPA mode serdes. This is why I am puzzled. I compile the example code from TI, and there is no error. Setting up pll and the altlvds_rx were done similar way.

    Ramakrishna
  • 0 in reply to Ramakrishna Bachimanchi
    TI__Guru* 91947 points

    Ramakrishna,

    Are you still having trouble with this?

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 300 points
    Hi Jim,
    yes. I got no where with altera forums too. I still get the error when I tried to compile the code which is similar to the test code provided by TI. Not sure, if I am missing something in the constraints file somewhere

    Ramakrishna