AFE5401-Q1: Trigger to DSYNC2 latency and digital output latency

Hello,

I am using the AFE5401-Q1 and I have a few questions regarding the devices Trigger to DSYNC2 latency and digital output latency.

This was the test setup for the first question, which is about the Trigger to DSYNC2 latency (TRIG_DSYNC2_LAT):

A 50MHz clock is fed into the AFE5401. The AFE5401 serializes the data of all 4 channels. The DELAY_COUNT setting is set to 1, which means a DELAY_PHASE of 2xt_{AFE_CLK}. I then measured the time it took from the Trigger Signal to DSYNC2 high.

1. Clock divider 3, decimation factor off. Sampling period: 60us. Trigger to DSYNC2 high measured at around 380us, subtracting the DELAY_PHASE this means 260us (4.3 times the sampling period).
2. Clock divider 2, decimation factor 2. Effective sampling period after decimation: 80us. Trigger to DSNYC2 high measured at around 440us, subtracting the DELAY_PHASE this means 280us(3.5 times the sampling period).
3. Clock divider 2, decimation factor 4. Effective sampling period after decimation: 160us Trigger to DSNYC2 high measured at around 880us, subtracting the DELAY_PHASE this means 560us(3.5 times the sampling period).

Table 22 in the data sheet describes the TRIG_DSYNC2_LAT for an AFE_CLK and 25 MHz (and probably with DELAY_COUNT to 0, which means a DELAY_PHASE  of 1). Is there a way to determine/calculate the TRIG_DSYNC2_LAT for other settings of the device, or should I use the measured ~3.5-4.3 (effective) sampling period and at this to the DELAY_PHASE?

For second part of questions:

The data sheet states states that there is a digital output latency of 10.5 t_{AFE_CLK} cycles from sampling to digitized output. Does this mean t_{AFE_CLK} cycles before or after decimation is applied? For example setup 2 from above: Is the digital output latency 420us or 840us?

Is there any interaction between TRIG_DSYNC2_LAT  and the digial output latency?

Used data sheet revision: SBAS619A –MARCH 2014–REVISED JUNE 2017

Kind regards,

Tobias