DAC7311: Output state concern when low and high level holding time is not enough

Hi

customer have another question as below:

we have another further question need your help on the DAC7311DCKR clock signal.

I find in the datasheet that, the CPOL bit  is 0, while CPHA bit is 1, and as I know in SPI definition, this may mean the Clock signal should be low level when idle ?please help confirm this.

Basing on our issue in customer side, in which the OVP is triggered when adjusting the output voltage from 18V to 19V, while the OVP point is 38V.  I have one concern, does the wrong clock signal logical level when idle  will cause this OVP if the  minimum SCLK high&low time is not met.

 

I conducted test with the SCLK logical level when idle following the CPOL is 0, CPHA is 1, and found if the SCLK high&low time not met, the SPI may fail to adjust voltage.

in customer side,  the SCLK logical level when idle is high , which may not follow the spec, and OVP triggered when SCLK signal high&low time not met.

 

so, would you please help confirm  if the wrong logical level when idle will cause the DAC output max voltage? which will cause voltage be adjusted to the maximum voltage and trigger OVP.

SPI Standards

Max,

The resolution of the oscilloscope capture you have shared is not sufficient for me to actually inspect any of the signals.

I do not feel like the datasheet is suggesting that it is required that SCLK idles high and that CPOL = 0 & CPHA = 1 are requirements. That section is simply proposing a configuration that WOULD work, but not that is required. The main requirement is that data is latched on the falling edge of SCLK. This implies that both CPOL = 0 & CPHA = 1 or CPOL = 1 & CPHA = 0 would work.

This perspective is reinforced by Figure 1 in the datasheet, which effectively illustrates SCLK optionally idling either high or low along with the timing specification t4 which indicates 0ns minimum time between SYNC falling edge and SCLK rising edge.

What is harder to deduce from the datasheet is whether the time from SYNC falling edge to the first SCLK falling edge needs to be greater than the standard setup time defined by t5 (5ns) since SCLK falling edge to SCLK falling edge is not defined as a timing requirement.

If you could please post a higher quality format of the oscilloscope capture you shared, it would be helpful for me to attempt to make some more informed observations. Even better would be a capture with time measurements between the SYNC falling edge and first SCLK falling edge in terms of replicating this on a bench setup or via simulation.

Certainly SCLK idling low would give more timing margin to the first SCLK falling edge, so this could conceivably be a factor though we cannot ascertain this from the datasheet as it is.