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ADS1298: 1 bit shifted received from AD1298 with MSP430F67651A

Ashish Jain99
Prodigy 130 points

Part Number: ADS1298

Hello,

I have done all the initialization of ads1298 and i can read registers wit POL=1,PHA=0,

when i read channel data which is C00000,8*(800000)

I do not get anything with this setting.

I am receiving wrong register data with recommended setting of POL=0,PHA=1.

when i read channel data which is C00000,8*(800000)

I get one bit shifted as 600000,8*(400000).  I have check those on DSO and the data is correct as C00000,8*(800000).

my be when i read registers those are also shifted values.

Please help...

Thanks,

Ashish Jain

  • 0
    TI__Guru 69076 points
    Hello Ashish,

    Thank you for your post.

    Can you please explain your question more clearly? I do not understand this notation: "C00000,8*(800000)". To clarify, you should always be using CPOL = 0 and CPHA = 1 for the ADS1298 interface.

    If the output is beginning with C0xxxxh, that is likely the beginning of the 24-bit STATUS word which preceeds the conversion data.

    In order to read registers, you must first exist the RDATAC mode by sending the SDATAC command first before any other commands.

    Best regards,
  • 0 in reply to Ryan Andrews
    Prodigy 130 points

    Hello Ryan,

    I am doing as you are suggesting and first 24 bit data is C00000 and next 8 24 bit datas are 800000, but as i told you when i read the buffer it shows me 600000 and 8 times 400000, which is 1 bit shifted.

    please lokk at screen shot of DSO for first byte above...

    thanks,

    ashish jain

  • 0 in reply to Ashish Jain99
    TI__Guru 69076 points

    Hello Ashish,

    Thanks for the explanation. I understand you are reading STATUS + 8 channels of data from the buffer. For your information, 800000h corresponds to the negative full-scale code for the ADC. Depending on the input conditions, that's probably expected.

    If you are using the correct SPI settings in your MCU (CPOL = 0, CPHA = 1), the data should be read correctly by the MCU. In your scope image, the waveforms show no significant delays. The rising edge of SCLK is shifting the data, and the falling edge should be used to latch the data. I would suggest that you probe the same signals at the input to your MCU to confirm there is no significant phase shift in the SPI signal path.

    What is the frequency and amplitude of your SCLK? It looks to be a little larger than 3.3 V peak-to-peak.

    Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 130 points

    Hello Ryan,

    I have checked the waveform and it is same as ADS1298 side.

    i dont know why it is little higher than 3.3V but i am supplying 3.3V exect to the controller.

    also

    when i read registers from ADS1298 , Garbage values are appeared in (CPOL = 0, CPHA = 1) mode.

    when i read channel data from ADS1298 , 1 bit shifted values are appeared in (CPOL = 0, CPHA = 1) mode.

    when i read registers from ADS1298 , correct values are appeared in (CPOL = 1, CPHA = 0) mode.

    when i read channel data from ADS1298 , no data (all zeroes) values are appeared in (CPOL = 1, CPHA = 0) mode.

    please help.

    Thanks,

    Ashish Jain

  • 0 in reply to Ashish Jain99
    TI__Guru 69076 points

    Hi Ashish,

    Ashish Jain99 said:
    I am doing as you are suggesting and first 24 bit data is C00000 and next 8 24 bit datas are 800000, but as i told you when i read the buffer it shows me 600000 and 8 times 400000, which is 1 bit shifted.

    Your scope capture shows the correct output waveform that would correspond to C0h as the first byte in the STATUS word. There appears to be no problem with the alignment of SCLK to MISO. If the data is being shifted in your MCU data buffer before you have the chance to read it, but that's not something I can help with.

    Please check the SPI timing requirements on page 17. Remember that there is a setup time required after /CS goes low before you can send SCLK (tCSSC).

    There's no need to experiment with different SPI mode settings - the ADS1298 interface is only designed to operate with CPOL = 0 and CPHA = 1.

    There may be other reasons to explain why conversion data looks like garbage. For example, if you are operating in RDATAC mode, the output shift register in the ADS1298 will be overwritten with new conversion data every time there is a /DRDY falling edge. If you are reading the previous conversion when a new /DRDY falling edge occurs, the very next SCLK will read out the MSB of the new conversion.

    Do the register contents seems to be shifted by 1 bit as well or do they not make any sense? Try reading all of the default registers after power up. If register contents are read back and do not make sense, make sure that:

    1. the device is placed in SDATAC mode first
    2. you are satisfying the tSDECODE timing spec

    Regards,