ADS54J66EVM: ADS54J66 ADC test mode peculiar behaviour.

Hi,

I'am using ADS54J66 evaluation board for JESD interface bring up using test patterns provided by the ADS54J66 ADC. link for the datasheet given below :

 http://www.ti.com/lit/ds/symlink/ads54j66.pdf.

I have made the setup by connecting the ADS54J66 eval board with  xilinx KC705 eval board and the ADC data is sent using JESD protocol using FMC connectors.

In KC705 eval board added JESD receiver core and AXI-stream FIFO and added stream signal to the chipscope and observed the data output on AXI-stream bus using chipscope below is the data observed on the AXI-stream bus of width 128.

In datasheet pg no 53 mentioned that different test patterns can be generated by the ADC chip.But not able to generate all mentioned test patterns mentioned in datasheet. Like

ADC page( 0Fh),register 74h.(7:4)

0000 = Normal operation using ADC output data - random data without adc input given.

0001 = Outputs all 0s  - Unable to generate.(00000000000000000000000000000000)

0010 = Outputs all 1s  - Unable to generate.(00000000000000000000000000000000)

0011 = Outputs toggle pattern: Output data are an alternating sequence of 101010101010 and 010101010101 - Able to generate(aaaa56555655aaaa5655aaaa5655aaaa)

0100 = Output digital ramp: output data increment by one LSB every clock cycle from code 0 to 16384 - Able to generate

0110 = Single pattern: output data are custom pattern 1 (75h and 76h)  - Unable to generate.(00000000000000000000000000000000)

0111 = Double pattern: output data alternate between custom pattern 1 and custom pattern 2 - Able to generate (but unable to generate when both the custom patterns are set to all zeros or all ones).

1000 = Deskew pattern: output data are 2AAAh - Able to generate (a8aea8aea8aea8aea8aea8aea8aea8ae)

1001 = SYNC pattern: output data are 3FFFh  - Unable to generate.(00000000000000000000000000000000)

can anyone explain the reason behind this peculiar observation.

Thanks in advance.