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DAC38RF82EVM: Question concerning the DAC38RF82EVM and Schematic

David Hildebrand
Expert 4860 points
Part Number: DAC38RF82EVM
Other Parts Discussed in Thread: DAC38RF82, DAC38RF83

Looking over the documentation for the evaluation CCA for the DAC38RF82 we have come across discrepancies and wondering if you could clarify?

Figure 20 in SLAU671A (http://www.ti.com/lit/ug/slau671a/slau671a.pdfdoes not match the schematic provided for the DAC38RF8xEVM board.  The resistor values for R211, R210, and R212 are not consistent between the two,.  Looking at the BOM’s for the 6 different DAC options, they all agree with the Schematic and not Figure 20.  We are wondering if the boards are built to the BOM’s or Figure 20? Additionally is the 16dBm input power based on the manual values for that input T attenuator.  Our calculations show a difference of about 7dB between the different resistance values in those spots.  I also notice the wording in  1.2.1.1 states that the default EVM is configured for single-ended clock but the schematic shows the single-ended path as DNI.

We are calculating that T1 should be driven between -1dBm and 7dBm based on the spec in the DAC38RF83 datasheet.  Based on the values from the BOM what does TI recommend we drive the J1 clock EVM with? 

E2E_Post_1.docx

  • 0
    TI__Genius 9695 points
    Hi David,

    1) Use the BOM and not the resistor values in figure 20 for the most up to date component values. The BOM has been updated several times since revision A of the EVM but the figure has not been updated.
    2) The 16dBm was based on lab testing of the EVM with an external 9GHz clock. We found this input power gave the most stable operation over temperature. Note that the DAC device requires about 2dBm. Most of the power is dissipated by the lossy resistive network at 9GHz.
    If you are building your own board, you can replace the resistive network with a 1:2 balun
    3)Yes, the single ended clock path is DNI on the EVM. The wording in section 1.2.1.1 is related to the EVM software. When the software is configured for external clock, it defaults to the single ended clock input.
    4)The input power to T1 will depend on the clock frequency. Refer to section 1.2.1.2 of EVM users guide which describes a clock mode (CMODE2) that uses less input power at J1.

    Thanks,
    Eben.