ADS127L01: Timing requirement

Hello Mochi,

Thank you for your post.

Mochi said:

Q1: On the datasheet Figure 85 shown, START ramp up command is during CLK Low state with tsu(st) setup time requirement.

Then what happen if we send START command as Figure A, The ADC can recognize START command at next CLK ramp up as B point?

Yes - if the rising edge of START occurs less than 10 ns before the rising edge of CLK, the device may not recognize the new START pin state until the next CLK rising edge (point B).

Mochi said:

Q2: Is this DS ADC's internal state-machine run to output /DRDY to Low following tsu(ST) + td(FILT) + td(NDR) processing time after detect START command?   No matter what is CLK status when send START command. 

The START command is decoded on the seventh SCLK falling edge. Then, the customer should expect to wait td(FILT) + td(NDR) before they see the next falling edge of /DRDY.

Mochi said:

Q3: In Figure 91, what if we input SCLK clock during tko time period, Is the ADC output /DRDY Low correctly?

During tKO, the device is trying to update the output shift register with new conversion data. If the user sends SCLK during the tKO period, the data may not be loaded correctly, causing the result to be corrupted.

Mochi said:

Q4: Is there timing requirement for "Red Line" period in Figure 91?

I do not believe there is any requirement here with respect to /DRDY. However, when /DRDY falling edge is detected in SPI mode, the user must observe a delay between /CS falling edge and first SCLK rising edge (td(CSSC)).

Best regards,