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Original question:

ADC128S102 - address register while #CS deasserted

ADC128S102QML-SP: Is address register while #CS de-asserted

Steven Smith1
Prodigy 10 points

Part Number: ADC128S102QML-SP
Other Parts Discussed in Thread: ADC128S102,

I read the question and answer for "ADC128S102 - address register while #CS de-asserted" and was wondering if TI will guarantee the behavior described instead of just saying "should". To re-state the question: When the CS is de-asserted and then later asserted, is the last value shifted into the control register retained for the first conversion data output?

Thanks!

Steve Smith

  • 0
    TI__Genius 17125 points

    Hi Steve,

    I did a search on the ADC128S102 and wasn't able to determine which post you mentioned.

    First off, be sure you are looking at the right part and datasheet.  The operation and performance of the commericial grade ADC128S102 and the space grade ADC128S102QML-SP are similar but there are a few differences.

    The part will operate as difined in the datasheet.

    The registers will refresh during each conversion cycle.   The conversion cycles will begin when CSb is deasserted.  If CSb is high and then toggled low, the channel sampled will be the channel programmed into the register during the previous sample cycle.   Note that a sample cylce must be 16 clock cycles or the registers will not be updated.

    Let me know if that answers your quetions.

    Kirby