ADS7952: ADC reading issue: Reading half values

Hi Goutam,

That sounds strange.  Are the codes exactly 1/2 of the expected values?  If so, check to make sure you're not toggling between the two analog input ranges (Vref vs. 2x Vref) which would this behavior.  

Hi Collin,

The Vref input to the ADS7952 is rock solid 2.5V, no change in that. Also all other input signals are at same level, may be slightly noise is added because of the loading. Do you see any improvement required in the Circuit attached below.. Any problem value changes required in ( resistor and capacitor) in the SDI, SDO and CLK lines.

Waiting for your response.

Thanks and Regards

Goutam

Hi Collin,

What is the sinking current of Ref pin of the IC. I saw in the datasheet suggested to add 100k resistor between PIN to the source of the reference signal. When I am powering from external source with 2.5V, it is drawing almost 300mA. Can it draw such a high current.

Can we have a call to discuss the issue in details.

My contact number is +91-9741201388.

Thanks and Regards

Goutam

Hi Collin,

Sorry for the wrong circuit attached. Please find the corrected circuit. Can we able to connect over a call or chat.

Thanks and Regards

Goutam

Hello Goutam,

1. SPI communication CLK is 20kHz; can be increased to 125kHz; Is this frequency is OK to operate?

Yes, the max SCLK rate is 20MHz, anything up to that is fine

2. Is the SPI CLK frequency is related to the MUX ADC channels sampling frequency?

Yes, the clock frequency controls both the data out throughput rate as well as the sampling rate of the device.

3. What are the possible conditions, when values read ½ of the expected values.

a. Per the previous response “check to make sure you're not toggling between the two analog input ranges (Vref vs. 2x Vref) which would this behavior”. Do you mean if any one channel ( out of 12) analog value, varies between 2-4V ( Vref= 2.5V and 2*Vref=5V) then ADC can read ½ of the expected values?

b. Any other possible conditions to read ½ values; temperature, PCB layout issues, CLK frequency etc?

This device has the option of changing the full scale input range, by changing DI6 when starting a conversion. This means that the Full scale input range can be 2.5V or 5V.  The channel outputs can vary if Vref (register DI6) is changed for each conversion. The full scale input range (FSR) can be changed to either 2.5v or 5V for each channel. This means that if the FSR is at 5V, but expected to be at 2.5V, an input signal of 2.5V will read at half digital output in reference to full scale. If the FSR is at 2.5V and an input signal of 2.5V is applied, then the digital output would be all 1’s.

If you are seeing all channel data out at half value, this could mean your timing is incorrect and missing the MSB of the data out. This would then reflect in all data out at half value.

4. The signal is getting filter using a RC filter with value 1k and 0.1uF and protected by BAT54S diode ( 3.3V pullup and ground pulldown), before giving to 12 ADC channel inputs. And No OPAMP is used between MXO (P.7) and AINP (P.6) before giving to the ADC. Is it ok use if all the signals are DC in nature.

This should be fine if the input signals are DC in nature. The capacitor is on the larger side, thus you might have some inaccuracies at start up as the cap is charging; with DC signals once the cap is charged, all should be fine

5. What is 100K series resistance recommendation for Vref Pin; not very clear.

Where did you see this? I cannot find this in the datasheet.

6. SPI communication side we have used 470R, 10K and 470PF capacitor; do they are ok or do have better recommendation.

The device can function without these components on the digital line, but they can be added if noise or reflection issues are expected.

Now, some questions for you

What mode are you using the device in?

Can you explain in more detail what you mean by "the device is loaded"?

Please provide a scope shot of at least 3 frames including the digital lines SDI,SDO,SCLK, CS

Regards,Cynthia

Collin Wells said:

Hi Goutam,

Thank you for confirming that you've resolved the high-current issue. In general don't apply voltage to pins of integrated circuits without first applying power.

There are only two reasons why you'd received exactly 1/2 the expected value:
1.) You're actually applying 1/2 the voltage you think you are... not happening in our case
2.) Coming back to my first post, you're not correctly configuring the analog input range and are toggling between VREF and 2xVREF modes (Range 1 / Range 2).... I have checked but that is happening with mean values, all are under 2V range; with adding some spikes it may cross 3V

3. GPIO2 PIN ( pin #1) need to grounded to get Range1?