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ADS122C04: ADS122C04 Data rate issue

Part Number: ADS122C04

Hello, I am writing a driver for the ADS122C04 and I have some interesting issues.

I first write and verify the contents of the four Configuration registers:

>>
DET ADC INIT    (ADDR: 80)
Verify ERR_NONE, reg:40, 01 -> 01
Verify ERR_NONE, reg:41, B2-> B2
Verify ERR_NONE, reg:42, 20 -> 20
Verify ERR_NONE, reg:43, 00 -> 00

Then I read out ten samples in one-shot mode by monitoring the nDRDY pin with an interrupt to understand the maximum sample rate that can be had in one-shot with repeated sends of start commands.

3595 ADC SAMPLE DATA: 115A3A
3646 ADC SAMPLE DATA: C66D3A
3698 ADC SAMPLE DATA: 40693A
3749 ADC SAMPLE DATA: 4C713A
3801 ADC SAMPLE DATA: 1B5D3A
3852 ADC SAMPLE DATA: 6653A
3904 ADC SAMPLE DATA: BB623A
3955 ADC SAMPLE DATA: 99663A
4007 ADC SAMPLE DATA: 865C3A
4058 ADC SAMPLE DATA: 69683A

The first number is the current OS time in milliseconds, and the final hexidecimal codes are improperly formatted adc samples (not the issue at hand).

As you can see in the configs, I am setting register $01 ( $41 to write, and $21 to read) to value B2, which should be 1000 sps, normal mode, single shot, external ref, temp sensor disabled.

but for whatever reason my data-rate remains at ~20Hz which is the default rate (Sample Time delta ~ 50ms). I tried to download the eval kit gui software to review the configuration that TI used to configure the part, but the only thing contained within the download zip is the build results from code-composer and the makefiles.

So my questions are as follows:

1 - am I misunderstanding the configuration process?

2 - does anyone have any reference code for this part?

Thanks in advance

  • For more Clarity, here is me manually starting a conversion showing that the configuration register changes without the sending of the start command.

    >> i2c read 80 21 1
    Aquire Result: ERR_NONE
    Read Result: ERR_NONE
    Address:80, Register:21, Data:00
    Release Result: ERR_NONE
    
    >> i2c write 80 41 C2
    Aquire Result: ERR_NONE
    Write Result: ERR_NONE
    Release Result: ERR_NONE
    
    >> i2c read 80 21 1
    Aquire Result: ERR_NONE
    Read Result: ERR_NONE
    Address:80, Register:21, Data:C2
    Release Result: ERR_NONE
    
    >> i2c read 80 21 1
    Aquire Result: ERR_NONE
    Read Result: ERR_NONE
    Address:80, Register:21, Data:C2
    Release Result: ERR_NONE
    
    >> i2c write 80 40 01
    Aquire Result: ERR_NONE
    Write Result: ERR_NONE
    Release Result: ERR_NONE
    
    >> i2c read 80 20 1
    Aquire Result: ERR_NONE
    Read Result: ERR_NONE
    Address:80, Register:20, Data:01
    Release Result: ERR_NONE
    
    >> i2c write 80 08 02
    Aquire Result: ERR_NONE
    Write Result: ERR_NONE
    Release Result: ERR_NONE
    
    >> i2c read 80 10 4
    Aquire Result: ERR_NONE
    Read Result: ERR_NONE
    Address:80, Register:10, Data:2C-31-28-00
    Release Result: ERR_NONE
    
    >> i2c read 80 21 1
    Aquire Result: ERR_NONE
    Read Result: ERR_NONE
    Address:80, Register:21, Data:01
    Release Result: ERR_NONE

    As you can see, at some point, Configuration register 1 at some point gets cleared out.

  • Hi Luke,

    Make sure the command you are sending is correct.  For example, 0x40 is a register write to configuration register 0.  0x41 is also a register write to configuration register 0, as is 0x42 and 0x43.  The correct usage is shown in the ADS122C04 datasheet on page 39.  Bits 3-2 are register address bits (indicated as 'rr' in the datasheet) and bits 1-0 are don't care bits (indicated as 'xx').  The WREG and RREG commands work the same way.  For example the WREG commands would address the this way:

    0x40 -- WREG register 0

    0x44 -- WREG register 1

    0x48 -- WREG register 2

    0x4C -- WREG register 3

    Best regards,

    Bob B

  • Bob,

    Thank you. I will continue with this register map;

    typedef enum
    {
        ADS122C04_REG_NONE     = 0x00u,
        ADS122C04_REG_RESET    = 0x06u,
        ADS122C04_REG_START    = 0x08u,
        ADS122C04_REG_PWRDN    = 0x02u,
        ADS122C04_REG_RDATA    = 0x10u,
        ADS122C04_REG_RCONF0   = 0x20u, /* composites for simplicity  (base cmd)*/
        ADS122C04_REG_RCONF1   = 0x24u, /* composites for simplicity */
        ADS122C04_REG_RCONF2   = 0x28u, /* composites for simplicity */
        ADS122C04_REG_RCONF3   = 0x2Cu, /* composites for simplicity */
        ADS122C04_REG_WCONF0   = 0x40u, /* composites for simplicity  (base cmd)*/
        ADS122C04_REG_WCONF1   = 0x44u, /* composites for simplicity */
        ADS122C04_REG_WCONF2   = 0x48u, /* composites for simplicity */
        ADS122C04_REG_WCONF3   = 0x4Cu, /* composites for simplicity */
    }ads122c04_reg_t;