Other Parts Discussed in Thread: ADS1262,
I am using python3 and RPI3 to access the serial data. I can read the analog signal correctly, from AIN2-AIN5, using either the internal or external reference (connected to ANI0-AIN1).
However, I am getting in trouble to set and read the correct diff voltage from the TDAC. I selected the MUX Input to TDAC (P&N), PGA=1, and set TDACP, TDACN values and enable OUTP and OUTN, I am getting ~5.25 V respect to the ground, on AIN6 and AIN7 pins. Consequently, the ADC reads nearly to 0 V.
I am powering the chip using single PS +5V.
The register configuration is below. I call each module sequencely and check if the registers have been update.The command SER.spi_init[], send list the serial data, 0x40, #Address, #Registers, New Register value.
def ADS126x_version(self): # ADS126x version and Revision
reg_addr_base = 0b00100000 # RREG(0x20)
reg_addr_sufix = 0b00000000 # 0x00
reg_value = [0x0000000] # 0x00
configuration = SER.spi_init(0, reg_addr_base, reg_addr_sufix, reg_value, self.speed)
time.sleep(0.1)
print('\033[34m' + "Chip Version= ", configuration[2]>>5, " Revision Number= ", configuration[2] & 0x1f, '\033[0m')
def ADS126x_pw_reg(self): # ADS1262 Power Register
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00000001 # 0x01
power_reg = [0b00000000] #0x00
configuration = SER.spi_init(0, reg_addr_base, reg_addr_sufix, power_reg, self.speed)
time.sleep(0.1)
def ADS126x_int(self): # ADS1262 Interface Mode Register
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00000010 # 0x02
int_reg = [0b00000100] # 0x04
configuration = SER.spi_init(0, reg_addr_base, reg_addr_sufix, int_reg, self.speed)
time.sleep(0.1)
def ADS126x_mode0(self): # ADS1262 Conversion Mode 0
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00000011 # 0x03
mode_0_conf = [0b00000000] # 0x00
configuration = SER.spi_init(0,reg_addr_base, reg_addr_sufix, mode_0_conf, self.speed)
time.sleep(0.1)
def ADS126x_mode1(self): # ADS1262 Conversion Mode 1 - Filter
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00000100 # 0x04
mode_1_conf = [0b10010000] # 0x90
configuration = SER.spi_init(0,reg_addr_base, reg_addr_sufix, mode_1_conf, self.speed)
time.sleep(0.1)
def ADS126x_mode2(self): # ADS1262 Conversion Mode 2
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00000101 # 0x05
mode_2_conf = [0b00000100] # 0x04 - PGA=1
configuration = SER.spi_init(0,reg_addr_base, reg_addr_sufix, mode_2_conf, self.speed)
time.sleep(0.1)
def ADS126x_mux(self, mux_ch): # ADS1262 Input MUX Register
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00000110 # 0x06
mux_inp = [0b11101110] # 0xEE - TDACP and TDACN
configuration = SER.spi_init(0,reg_addr_base, reg_addr_sufix, mux_inp, self.speed)
time.sleep(0.1)
def ADS126x_ref_mux(self): # ADS1262 Reference MUX Register
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00001111 # 0x0F
refmux_inp = [0b00001001] # 0x09 - AIN0 - AIN1
configuration = SER.spi_init(0, reg_addr_base, reg_addr_sufix, refmux_inp, self.speed)
time.sleep(0.1)
def ADS126x_tdac_vp(self): # ADS1262 DAC Volt Pos Register
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00010000 # 0x10
tdacp_inp = [0b00000111] # 0x07 - 3.0 V
tdacp_Rec = SER.spi_init(0, reg_addr_base, reg_addr_sufix, tdacp_inp, self.speed)
time.sleep(0.1)
def ADS126x_tdac_vn(self): # ADS1262 DAC Volt Neg Register
reg_addr_base = 0b01000000 # WREG(0x40)
reg_addr_sufix = 0b00010001 # 0x11
tdacn_inp = [0b00011001] # 0x19 - 0.5 V
configuration = SER.spi_init(0, reg_addr_base, reg_addr_sufix, tdacn_inp, self.speed)
time.sleep(0.1)
def ADS126x_cal(self): # ADS1262 calibration Register
reg_addr_base = 0x40 # WREG(0x40)
reg_addr_sufix = 0x07
OFCAL0 = [0x00] # [0xEF] 200 mV # 0x00 reset
SER.spi_init(0, reg_addr_base, reg_addr_sufix, OFCAL0, self.speed)
reg_addr_sufix = 0x08
OFCAL1 = [0xD0] # [0x47] 200 mV # 0x00 reset
SER.spi_init(0, reg_addr_base, reg_addr_sufix, OFCAL1, self.speed)
reg_addr_sufix = 0x09
OFCAL2 = [0x00] # [0x07] 200 mV # 0x00 reset
SER.spi_init(0, reg_addr_base, reg_addr_sufix, OFCAL2, self.speed)
reg_addr_sufix = 0x0A
FSCAL0 = [0x00] # 0x00 Gain 1
SER.spi_init(0, reg_addr_base, reg_addr_sufix, FSCAL0, self.speed)
reg_addr_sufix = 0x0B
FSCAL1 = [0x00] # 0x00 Gain 1
SER.spi_init(0, reg_addr_base, reg_addr_sufix, FSCAL1, self.speed)
reg_addr_sufix = 0x0C
FSCAL2 = [0x39] # 0x40 Gain 1
SER.spi_init(0, reg_addr_base, reg_addr_sufix, FSCAL2, self.speed)
reg_addr_sufix = 0x0D
IDACMUX = [0xBB] # 0xBB reset
SER.spi_init(0, reg_addr_base, reg_addr_sufix, IDACMUX, self.speed)
reg_addr_sufix = 0x0E
IDACMAG = [0x00] # 0x00 reset
SER.spi_init(0, reg_addr_base, reg_addr_sufix, IDACMUX, self.speed)
reg_addr_sufix = 0x12
GPIOCOM = [0x00] # 0x00 reset
SER.spi_init(0, reg_addr_base, reg_addr_sufix, GPIOCOM, self.speed)