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ADS1271: Unsteady data and occasional error peaks

Part Number: ADS1271

Hi,

i have been struggling for many days now trying to successfully read out sensor data converted by the ADS1271 Converters. Purpose of the board that i am trying to get run is to conduct precise and fast power consumption measurements. For this purpose i am utilizing 2 current sensors (LEM LESR 50) and a shunt resistor next to a voltage divider. For the ADC conversion i am thus using 4 ADS1271 in a daisy-chain configuration (SPI format) (schematics attached). My issue is that i am not able to receive steady and precise measurements on all 4 ADS1271 and that i get strong and repeating error peaks in the conversions of the 3 latter ADS1271 in the daisy-chain configuration (data value plots attached). I have tried so many ways to solve this already and thus have wasted several days and i just do not know how to take this further.

I have also attached a couple of oscilloscope shots (SCLK and MISO, CLK, ~DRDY on 2 ADS1271, Current Sensor Analog Output, Shunt Sense Analog Output).
(Regarding attached files: adc_history corresponds to voltage divider; adc_history2 corresponds to current sensor readings; adc_history3 corresponds to current sensor readings with 0 current consumption over it)
I would be quite glad if someone could provide me a helpful hint. If further information and/or data is needed to get a better picture on my setup, please feel free to ask.

Thanks in advance.

Best regards,

dropbox png files:

zip:

ads1271 data.zip

  • further hint on ~drdy shots: ~drdy_1 corresponds to inactive MCU; ~drdy_2 and ~drdy_3 whilst MCU is active.
  • Hello Mu,

    Welcome to our forum and thank you for your post!

    I can see in the ~DRDY2 and ~DRDY3 images that your SPI transactions are overlapping /DRDY falling edges. The falling edge of /DRDY marks the time that new data is available to read from the output shift register. You must finish reading data from all ADS1271 devices before the next falling edge. Otherwise, the data you read out will be corrupted by a mix of old and new data.

    Best regards,

  • Hello Ryan,

    thank you for your quick and helpful reply. I was able to solve that. But there's one thing that still bugs me: My data in my opinion is still too unsteady and i do only get meaningful data whenever i receive data on the falling edge of SCLK contrary to what is recommended in the datasheet (receive data on the rising SCLK edge) (data output for receiving on rising and falling edge are each attached). I have also attached oscilloscope shots of ~DRDY (on two ADS1271), MISO and SCLK and ~DRDY and SCLK. 

    So i would like to know: How do i manage to receive steady and clean data and wether it is feasible to receive data on the falling instead of on the rising edge of SCLK.
    Regarding the attached files: adc_history1: receiving on rising edge; adc_history1_rec_on_fall: receiving on falling edge; 

    Thanks in advance!

    Best regards,

    zip file:

    further data.zip

    dropbox link: see above.

  • Hi Mu,

    I'm glad you solved the first issue!

    Verify that your SPI timing meetings all the requirements on page 6 of the datasheet. Pay special attention to tDS and make sure you are latching the MSB of each device correctly.

    The daisy-chain section of the datasheet on page 27 gives more specific details regarding daisy-chain device connections and a calculation for the SCLK frequency required for the number of devices used and their data rate.

    Regards,
  • Hi Ryan,

    thank you a lot for the helpful hints and sorry for my lack of experience. The issue was that there was a lot of jitter in the generated SCLK signal (+-5 ns and more). So i lowered the bus speed down to 24Mhz.

    Best regards,
  • No problem at all, Mu! We're happy to help.