Part Number: ADS1283
Hi,
We are using the ADS1283 in a data acquisition system that is synchronized to a GPS disciplined rubidium oscillator. The ADS1283 is synchronized on the leading edge of the GPS 1 PPS signal using ADC in pulse sync mode. We apply the sync pulse tdr time prior to next rising edge of PPS so that the first DRDY signal should hit the 1PPS edge at the correct time.
ADC setup:
-Sampling frequency: 500Hz
-ADC clock 4.096MHz
-Filter: SINC+FIR, linear phase,(constant group delay 31 samples)
tdr=62,98046875/500)+(468/4096000)= 126.075ms
The sync pulse is synchronized with the adc clock so that we avoid hitting the “bad spot” tCSDL (±30ns adc clk rising edge window) mentioned in the datasheet.
The falling edge of the DRDY signal hits the 1PPS every 500 samples as expected, confirmed by scope measurement.
So far so good.
We tested the timing by applying a 1ms wide pulse on the ADC input centered 500ms after the GPS 1PPS trigger.
We assumed that we would see the center of the pulse exactly on sample no 1562 after the 1PPS rising edge on our recorded data.
A time series plot of the recorded samples shows that the pulse centre was between 1562 ms and 1564 ms and closer to 1562. Analysing the phase of the pulse shows that the pulse centre was 1562.448 ms. We understand that input circuitry does have certain impact on the added delay but 447us is much.
Is there any reason why our 1ms pulse center do not hit the 1562 sample but measure an extra phase delay of 447us?
Is there another simple way to test the sync timing?
Cheers,
Terje
