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ADS1282: ADS1282 stops DRDY falling edge after a while

Deniz Balaban
Prodigy 20 points

Part Number: ADS1282

Hello TI team,

I am sorry if this question asked before.

I designed a DAQ with 9 ADS1282 and I group them 3 by 3.(Same ADC Clock, SPI clock, reset, sync and power down) My opening sequence is:

power on:
sync='0'
reset='1'
power down = '1'

Wait for 100 ms
reset ='0' for 4.4 usec

Wait for 100 ms
sync = '1'

I do not change any configuration on ADC's and want to read them with default configuration.

After a while(less then 200ms) ADC's stops conversation. No more drdy falling edge.

Do I miss any basic concept?

  • 0
    TI__Mastermind 44820 points
    Hi Deniz,

    Welcome to the TI E2E Forums!

    Do you happen to have a schematic of your circuit that you could share?

    The only thing I might check on from your start-up description is the SYNC pin timing (see e2e.ti.com/.../2444790 for more details). You might need to toggle the SYNC pin more than once to ensure that the ADCs get synchronized.

    Apart from that issue, do be aware that after synchronization it will take ~63 conversion periods before the next /DRDY falling edge due to the conversion latency of the FIR filter.
  • 0 in reply to Christopher Hall
    Prodigy 20 points

    Thank you for fast reply,

    I attached my DAQ's 3 channel schematic design. I tried to use SYNC pin timing as you mention, but nothing changed. I also tried to change my power on sequence as:

    Power on

    SYNC = '0'

    Enable = '1'

    wait for 100ms

    Enable = '0' for 20 fclk period

    wait for 100ms

    start toggling SYNC(I change the state of SYNC when falling edge of fclk)

    high for 4 fclk period, low for 4 fclk period (repeat this 3 times and hold SYNC '1')

    wait for 100ms

    Then my reading procedure starts in here;When falling edge of DRDY catched I tried to read data.

    Other design timing values:

    Fclk period is 244.208 ns

    Falling edge of DRDY to first rising edge of the SCLK is 3.92 usec

    SCLK period 1.92 usec

    Last falling edge of SCLK to first rising edge of SCLK is 3.9 usec(Between two bytes)

    Free Documents.pdf

    Free Documents.pdf

  • 0 in reply to Deniz Balaban
    TI__Mastermind 44820 points

    Hi Deniz,

    Thanks for sharing a schematic!

    Have you tried powering up the device, setting the /RESET and /PWDN pins high and the SYNC pin low, to see if the issue occurs irrespective of issuing the SYNC command? In other words, do the ADCs stop responding on their own after a certain amount of time, or do they only stop responding after toggling the SYNC pin?

    Looking at the schematic, I was initially concerned about the quality of the +/- 2.5V supplies going to the ADC. Typically, LDOs are used to provide these supply voltages and you'd want to have decoupling capacitors on these supplies (and also between VREFP and VREFN) to help stabilize these supplies. I would recommend probing these supplies to see if you can observe any glitching or droop that might be powering down the device.

    Finally, double check on the CLK, /RESET, and /PWDN signals to see if these signals are still present and not floating after the ADC stops responding. If the ADC is powered, has a clock source, and the GPIO pins are set to enable the device, you should be getting a regular /DRDY signal.