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DAC38J84: sending of data with 4 LANE mode and JESD204B Frame Assembly Byte Representation(LMF:421)

pradeep chavana
Prodigy 10 points
Part Number: DAC38J84
Other Parts Discussed in Thread: ADS54J66, ADS54J66EVM,

1)the datasheet provide page 31 table 10 says JESD204B Frame Assembly Byte Representation(LMF:421) for dual channel,internal architecture page -24 functional block diagram  says, A,B,C,D channels ,but in   page 31 it say I0,Q0,I1,Q1,I2,Q2,I3,Q3, that means each individually chaneel is consider as  I and Q and what will be maximum out of the dac if the sampling of the dac is 2.5Gsps

2)in functional block diagram page -24  we have seen the in put muxing and out put muxing in the devices is this are configurable,ie means can we same Data to all the dac  out put are these data can be interlived also.

  • 0
    TI__Guru* 78154 points
    Pradeep,
    1. For dual channel mode, only 2 data paths are available. You may use the data path as two independent channels (i.e. A or B), or use the data path as I/Q signal path. Most of the signal chains processing blocks such as NCO and QMC are designed for quadrature upconversion.
    For quad channel, you may have 4 data paths, either use them as all four independent channels, or 2 pairs of I/Q data.
    2. you may use the input and output mux to mux the data path around. The input and output mux can also "copy" the same data path around for debugging purpose.
    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 160 points

    Kang Hsia,

    Our requirements:

    DAC sampling Rate: 2.4GSPS

    DAC Mode: IQ Mode Dual Channel

    No of Lanes:4 lanes

    JESD204B Frame Assembly Byte Representation (Dual-Channel) for (LMF =421)


    1. In order to send the data to DAC in IQ dual channel mode using JESD204B, the frame assembly shown in above fig is correct?  (The first column is ch1 data , second column is ch2 data, third column is ch1 data and fourth column is ch2 data ... so on.)

    2. If we want reset the NCO using Sysref signal  during the operation by  configuring the config31 register is suffient ?


    3. If we can reset NCO using Sysref signal during operation, then how many clocks it will take to reset NCO frequency? Can you provide the timing diagram for NCO reset using sysref signal?

    4.In DAC38J84 datasheet, for SPI configuration of rDAC internal register . If we are using 7 bit address , then how can we have config127 register with 0x80 address?


    5. If we want to use DAC in IQ mode with 4 Lanes (LMF=421) then the following representation of IQ channel data is correct?


  • 0 in reply to Hassen Basha1
    TI__Guru* 78154 points

    Hi

    Hassen Basha1 said:
    1. In order to send the data to DAC in IQ dual channel mode using JESD204B, the frame assembly shown in above fig is correct?  (The first column is ch1 data , second column is ch2 data, third column is ch1 data and fourth column is ch2 data ... so on.)

    Yes, the above figure is correct. "I" stands for Ch 1, while "Q" stands for Ch2 data pattern. The numbering at the end (i.e. I1, Q1, I2, Q2, I3, Q3, I4, Q4) is the sample number with respect to time. It continues to increase with respect to time.

    Hassen Basha1 said:
    2. If we want reset the NCO using Sysref signal  during the operation by  configuring the config31 register is suffient ?

    yes, you will then need to trigger SYSREF pulse going into the SYSREF receiver circuit (SYSREFp/n) in order to reset the NCO counter properly. See following app note for detail:

    Hassen Basha1 said:
    3. If we can reset NCO using Sysref signal during operation, then how many clocks it will take to reset NCO frequency? Can you provide the timing diagram for NCO reset using sysref signal?

    We will have to measure and get back to you

    Hassen Basha1 said:
    4.In DAC38J84 datasheet, for SPI configuration of rDAC internal register . If we are using 7 bit address , then how can we have config127 register with 0x80 address?

    This is a typo. It should be 0x7F.

    Hassen Basha1 said:
    5. If we want to use DAC in IQ mode with 4 Lanes (LMF=421) then the following representation of IQ channel data is correct?

    It should be the following. The output may be "copied" to output Channel IoutC and IoutD if needed through output mux configuration.

  • 0 in reply to Kang Hsia
    Prodigy 160 points

    Thank you Kang Hsia.

    Please provide the timing diagram of nco reset using sysref signal at the earliest.

  • 0 in reply to Kang Hsia
    Prodigy 160 points

    Kang Hsia

    For the following question

    5. If we want to use DAC in IQ mode with 4 Lanes (LMF=421) then the following representation of IQ channel data is correct?

    Two IQ Input Channels (I1,Q1 for channel1 and I2, Q2 for channel2)  and two channel real outputs (Example A B or CD Channels)

    Summation of I1 and Q1 takes place in the summer block shown in figure (I1+Q1), similarly, the summation of I2 and Q2 channels takes place in the summer block (I2+Q2). The sum outputs (I1+Q1, I2+Q2)  is passed through the filter (x/sinx) , fractional delay and output mux fed to 16-b DAC (A or B or C or D depending on output mux selection). The input to 16-b DAC is real data and output of 16-b DAC is also Real output. 

    We want to use go with following approach

    Two channels IQ data as input  (I1,Q1 -channel no 1, I2,Q2 -channel no 2)

    Final DAC output is 2 channel Real analog output (CH1 and CH2).

    Please suggest whether the above approach is correct? 

  • 0 in reply to Hassen Basha1
    TI__Guru* 78154 points
    Hassen,

    Your latest picture is not correct. There is simply no I2 and Q2. I have already posted my drawing regarding the last numbering being the sample number with respect to time. Please refer to my last post for detail.
    -Kang
  • 0 in reply to Kang Hsia
    TI__Guru* 91947 points

    Hassen,

    The NCO takes about 457 clock cycles to update after a SYSREF pulse. See attached view. This shows a single pulse of SYSREF and the DAC output. The NCO was running at 1MHz then switched to 5MHz after the SYSREF pulse. The total time for this update was 620ns. The DAC Clock was running at 737.28MHz.

    Regards,

    Jim


  • 0 in reply to jim s
    TI__Mastermind 44680 points
    Hi Hassen
    Nothing has been posted since May 21.
    Do you need any other information on this topic, or is this thread resolved?
    Best regards,
    Jim B
  • 0 in reply to jim s
    Prodigy 160 points

    Hi Jim,

    Whether the  NCO update timing with respect to Sysref is always fixed at 457 clocks ? or it will change with each sysref pulse.

    Regards,

    K  Hassen Basha

  • 0 in reply to Kang Hsia
    Prodigy 160 points
    Hi Kang,
    How to use the summer block which is located just before the AB QMC Gain and Phase block. If I want use this summer block to sum I, Q channels data (I+Q) and send the real data to DAC input.
  • 0 in reply to Hassen Basha1
    TI__Guru* 91947 points
    Always fixed.
  • 0 in reply to Hassen Basha1
    TI__Guru* 78154 points

    Hi Hassen,

    this is where you can utilize the DAC38j84 GUI:

    inside the gui, you may automatically configure the device. The summing block is over here

    on the lower left hand corner, you may double click and get the register settings.

  • 0 in reply to Hassen Basha1
    Prodigy 160 points

    Hi,

    I Need some clarity regarding the interposer card(TSW14J10) interfacing with various EVM’s. Below are the evaluation modules which we are using:

    1)      FPGA Evaluation module – Virtex-7 FPGA VC709 connectivity Kit

    2)      ADC – ADS54J66EVM – ADS54J66 high speed, JESD204B interface ADCs

    3)      DAC – DAC38J84EVM – DAC38J84 high speed, JESD204B interface DACs

    For module level testing we need to interface FPGA EVM with the ADC & DAC EVM for which we have identified an interposer card(TSW14J10) and need a confirmation whether we can go ahead with the same or are there any other interposer cards which are better suitable for the EVM’s mentioned above.