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ADS1278: data read wrong in Frame-sync

Part Number: ADS1278


Hi,

There is something wrong in reading data from ads1278 in Frame-sync mode.

Firstly, the configures are listed as table 1. And scope of SCLK,  FSYNC, DOUT1, DATA_IN is pictured as figure 1.

FORMAT[2:0] 011
MODE[1:0] 00
PWDN[8:1] 00000001
FCLK 25M
CLK 6.25M
Vref 2.5V

          tabel 1

figure 1

The problem is that when DATA_IN is +2.5V, the date that i read is 0x031000, not like the datasheet is 0x7fffff; And DATA_IN is -0.5V, the date that i read is 0x327100. So in this situation i can't identify the positive or negative of the DATA_IN voltage. And the data that i read is very steady. 

In order to apply more information, the data of different DATA_IN is listed as table 2.

DATA_IN data
2.5V 0x031000
2V 0x348000
1.5V 0x675000
1V 0x9a6000
0.5V  0xcd3000
0V  0xff2000
-0.5V 0x327100
-1V  0x65a000
-2V  0xca6000
-2.5V  0xfca000
  • Hi Xiao,

    Welcome to the TI E2E community!

    When using Frame Sync mode, SLCK must continuously run for proper operation and be in sync with the master clock FCLK.  Based on your above waveforms, it looks like the SLCK does not meet this requirement.  Please take a look at page 9 in the datasheet for full timing requirements.

    Since you are running Fclk at less than 27MHz, you can also use SPI mode, which does allow the SCLK to be non-continuous.

    Regards,
    Keith N.
    Precision ADC Applications

  • Hi, Keith

    I have solved this problem by modified my codes. The new codes made the signals meet this requirement.

    Why i want to use FRAME-SYNC mode? Because i want to use the 37M FCLK input, i just want to test my code.

    Anyway, Thanks.