VSP5610: Not able to recover full cycle sine wave at the output of AFE.

karan jasani

Part Number: VSP5610

Hi,

We are using VSP5610 AFE to capture analog input from function generator i.e. Sine wave, Ramp etc.

We are using 1 MHz sampling clock and applying 1 KHz of sine wave with 1 Vpp and 2 V offset at the analog input pin of the VSP5610.

At the output digital side we are getting sine wave with only half cycle where as half cycle gets clipped. We are using SH mode.

How to recover full sine wave at the digital side ?

over 6 years ago

0 Alex Bhandari-Young over 6 years ago

TI__Mastermind 25895 points

Hi Karan,

Please refer to the Sample Hold (SH) Mode section of the datasheet and make sure you are following all the setup and configuration correctly for this.

Can you please let me know

What is the VCLP you have set?
What are you doing with AINGND?
What is the setting for SH_REFx_EN?
Is the input couple with a capacitor or DC connected?
Can you additionally share the full register configuration you are using?
Also the circuit diagram may help as well.

Best,

Alex

0 VISHAL KALWANI over 6 years ago in reply to Alex Bhandari-Young

Intellectual 705 points

VCLP IS 0.5V.THAT IS INTERNAL REFERENCE IS USED.
AINGND IS GROUND VIA CAPACITOR.
SH_REFx_EN IS ENABLED
INPUT COUPLE WITH CAPACITOR.

0 Alex Bhandari-Young over 6 years ago in reply to VISHAL KALWANI

TI__Mastermind 25895 points

Hi,

Let's take this to email. Can you send me an email at bhandari at ti.com?

Best,

Alex

Data converters

Data converters forum

VSP5610: Not able to recover full cycle sine wave at the output of AFE.