• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 49 subscribers
  • Views 438 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF83: start-up behaviour

vic zap
Intellectual 740 points

Part Number: DAC38RF83

Hi!

The recommended start-up sequence of the DAC38RF83 is described on the fig.167. Can you tell, please, how does the DAC behave in the period of time when the supplies are already provided, but the resetb pulse is not yet provided? Are the DAC registers initialized at power-up or filled with random values? Does the DAC try to operate in accordance with the randomly initialized regs during this period of time? Can the resetb pulse be delayed to an undefined time or it should be done as soon as possible after providing supplies to prevent unpredictabe operation of the DAC?

Regards, Victor.

  • 0
    TI__Genius 12780 points

    Hi Victor,

    One of our device experts is looking into your questions, and will be back with you soon.

    Best Regards,

    Dan

  • 0
    TI__Guru* 91947 points

    Victor,

    After power up, if the reset is not applied, the registers are in an unknown state. It is recommended to issue a reset as soon as possible to place the part into an initialization state. It is also recommend to keep TXENABLE low to force the DAC to midscale until the part is up and running properly. If you do not have a connection to the external TXENABLE pin, there is an internal pull down keeping this input low. The user would then override this by setting TXENABLE high in software after the part is configured.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 740 points

    Thanks for the reply.

    Is the resetb circuitry level sensitive or it requires an edge (rising/falling)? Can I place a 1kOhm pull-down resistor on the resetb pin to overcome internal 10k pull-up so that to keep the DAC in the reset state after power-up while my FPGA not yet configured?

    Regards, Victor.

  • 0 in reply to vic zap
    TI__Guru* 91947 points

    Victor,

    The reset needs to be a pulse and this must be at least 25ns wide. You can place a 1K pull down as long as you can still drive this input to a logic high.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 740 points

    Jim,

    If I've understood correctly, just by pulling down the resetb upon power-up, the DAC is not put in the reset state, it still stays in an undefined state. Therefore there is no sense to have a pull-down resistor on the resetb, since it doesn't change anything. Is it correct?

    Regards, Victor.

  • 0 in reply to vic zap
    TI__Guru* 91947 points

    Victor,

    Keeping reset low at power up will force the registers to their default setting. But not every register has reset control so there is a chance something may still come out of the DAC in the reset mode. This is why we recommend keeping TXENABLE low until the DAC is configured and up and running.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 740 points

    Thanks a lot, Jim, for the replies. Now it's clear.

    Regards, Victor.