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ADS1675: Data Rate setting and AD conversion rate

user6070365
Prodigy 10 points
Part Number: ADS1675

Hello,

In the reference document for ADS1675, on Table 1. Noise Performance, it states the data rate when fclk is 32MHz. Accordingly, I figured that by lowering fclk I could lower the Data Rate.

With the DRATE bits at 001, will the following be possible? If not, is there a way to get the Data Rate to 320 kSPS?

fclk = 20.48 MHz

Data Rate = 320kSPS

AD Conversion Data = 24bit

AD Conversion Rate = 7.68 MHz

Thanks!

  • 0
    TI__Mastermind 46430 points

    Hello,

    Welcome to the TI e2e community.

    Yes, you can run the master clock at a lower rate to adjust the output data rate.

    You will need to operate in DRATE mode 010, which is an oversampling ratio of 64.  (500ksps data rate with fclk=32MHz)

    The clock rate needed for 320ksps will be 64*320ksps=20.48MHz.  This will provide 24b conversion data.  The input modulator rate will be equal to Fclk, which in this case will be 20.48MHz.

    Regards,
    Keith N.
    Precision ADC Applications