ADC12DJ3200: ADC Sampling

Hi Ayesha

Please provide the following details:

1. What is the ADC clock frequency?
2. What is the register programming settings/sequence for the ADC? In particular, what is the JMODE setting?
3. Is the input frequency 2.1 GHz or 100 MHz?
4. What type of input signal path is used? A balun?
5. Can a schematic of the signal path or all ADC connections be provided?

Best regards,

Jim B

Hi Jim,

Please find the response below:

1. What is the ADC clock frequency? - 4.2Gsps (Interleaved Mode)
2. What is the register programming settings/sequence for the ADC? In particular, what is the JMODE setting? ADC set to J Mode 1
3. Is the input frequency 2.1 GHz or 100 MHz? 100 MHz
4. What type of input signal path is used? A balun? Balun BAL-0009SMG
5. Can a schematic of the signal path or all ADC connections be provided? Attached

Regards,

AyeshaADC_SCH.pdf

Hi Jim,

Also, in absence of the RF input, fs/2 component is very pre-dominant. The ADC is set to JMODE 1 and K is set to 5. Please find the plot of the signal taken without the RF input  ADC_4a_plot_without_signal.pdf

Hi Ayesha

Is this same behavior seen on multiple boards? Or is it just this one ADC on a single board that shows the odd behavior?

Can you share the register settings you are programming to the ADCs? Are you writing the same values to all ADCs?

Can you confirm the power supply voltages to the problem ADC are within specification?

Best regards,

Jim B

Hi Jim,

We do not have the same behaviour on all the boards. Its only one of the 5 cards is behaving this way.

All cards have the same code and configuration. Please find the ADC register values below:

The ADC supplies are within the specified range.

    x"000080",
    x"002900",  
    x"002A00",
    x"0030C4",
    x"0031A4",
    x"0032C4",
    x"0033A4",  
    x"004801",
    x"006001",
    x"020000",   -- Disable JESD 
    x"006100",    -- stop calibration
    x"020101",   -- Jmode 1 is selected
    x"020204",   -- Program KM1 (K-1) , K = 5, KM1 = 4
    x"020403",   -- Scrambler enabled, signed 2's complement data format, ~SYNCSE used as ~sync
    x"020500",
    x"020600",   -- DID = 0
    x"0211F2",
    x"0212AB",
    x"02130F", 
    x"006101", 
    x"020001",
    x"021602",
    x"021902",
    x"022000",
    x"022100",
    x"022200",
    x"0223C0",
    x"02B000",
    x"02B105",
    x"02B500",
    x"02B600",
    x"02B700"
  

Hi Jim,

We got the X-ray done and everything seems to be fine. Please find the X-Ray image attached for reference.

This seems to be an issue with internal ADC offsets. The Fs/2 component came down to -60dBFs on manually adjusting the offset registers. Now the Fs/4 and Fs/2-Fin  Component is still prominent at -45dBFs. We are trying to tune the ADC timing registers. 

Of the total 40 ADCs used in the project, 3 ADCs have the same issue. There seems to be an issue with default factory trim settings(Offset/ ADC timing). Please let us know the reason for this.

In one of the ADCs the Analog input captured is at -45dBFs for 0dBm input. Please suggest how to take this further.

Regards,

Ayesha

Hi Ayesha

I have reviewed your schematic and register settings. The schematic details shown look fine. 

The register settings also look OK, but I would add the following sequence at the end to trigger a new calibration. Performing a calibration is required to reach optimal performance. For the single input modes the process will match the gain of the converters which will minimize any gain related Fs/2-Fin spurs.

    x"006C00",  -- clear CAL_SOFT_TRIG
    x"006C01",  -- set CAL_SOFT_TRIG

The offset matching between converters is generally quite good and large Fs/2 spurs are therefore unexpected. You can try setting CAL_OS = 1 (Register x"006205") before doing the calibration to see if that improves the Fs/2 levels. Please note that using CAL_OS = 1 requires the input signal to be turned off, or the user must ensure the input signal has no content near DC or signals that would alias near to DC. See Offset Calibration in the datasheet for more information on this.

I would also closely inspect the input and output terminal connections for the BAL-0009SMG components. I have seen problems with soldering cause open circuits at those connections, which could cause the low signal levels seen in one of the boards.  I think it is possible that marginal connections could also cause problems with input signal balance, which would cause degraded HD2 performance. 

If you are using the ADC12DJ3200 device with 2.1 GHz clock rate, the factory trim settings for interleave timing may not give the best performance. This will result in increased levels of the Fs/2-Fin spur. You can re-adjust the trim setting to improve this spur level. 

The timing re-adjustment process for JMODE1 is as follows:  When single input, Foreground Calibration mode is used the TADJ_A_FG90 setting at register 0x0080 can be adjusted to reduce timing mismatch and reduce the Fs/2-Fin spur level. Read the value currently programmed in that register, and increase or decrease the value slightly to find the point where the Fs/2-Fin spur level is minimized. The value will likely only need to change by 10-20 steps to improve things.

I hope this is helpful.

Best regards,

Jim B