ADS124S06: Gain Calibration

Hi Burak,

I still don't know detail on what you are trying to calibrate.  Let me use an example where I want to measure a +/-20V input voltage using the ADS124S06.  Using an analog supply of +/- 2.5V, and the internal reference (also 2.5V).  The maximum input voltage that I can apply to the analog inputs is 2.5V and 2.5V is 1/8 the total input voltage. So I would need to create a voltage divider where 1/8 of the voltage is dropped across the resistor I wish to measure.  If I could have any value I wanted, I might pick 7k and 1k Ohm resistors and I would measure across the 1k.  If my resistors were 0.1% tolerant, I might have a situation where the 7k resistor is -0.1% (6993 Ohms) an the 1k resistor +0.1% (1001 Ohms).  The voltage divider in this case would have a voltage across the 1k as Vin(1.001k/(1.001k + 6.993k).  For a 20V input, the voltage across the resistor is now 2.5044V (instead of the desired 2.5V).  I would like to run the SYGCAL so that at a full-scale input of my system (which is 20V) I have a compensated response so that my calculations are still using a value of 2.5V as the reference, but I get an adjusted value due to the skew in the input voltage.  In other words, I want to see 0x7FFFFF for the full-scale reading in the output code.

This higher than expected input voltage will be ok when using the PGA disabled as I have not exceeded 50mV above the AVDD positive supply rail (assuming that the supply it is exactly at 2.5V).  However, even though I have not exceeded the absolute maximum input to the device, I will have an error if I enable the PGA.  The calibration will take place, but instead of calibrating the input voltage to the PGA, I will actually be calibrating to the output voltage of the PGA.  As the PGA is operating in a non-linear region I will also have compounded the error.

If instead I use a resistor that is slightly lower than 1k, I can avoid the over voltage input condition.  Now, this type of calibration is using the SYGCAL.  This calibration can also be accomplished using a point-slope method where the calibration gain slope is externally determined where y = mx + b.

See my remaining responses below.

Best regards,

Bob B

burak balkuv said:

"If you want to use the PGA, then I would suggest that the resistor divider be adjusted so that the input is always equal to or less than AVDD-0.15V."

a) Does that mean with a +/-2.5V supply internal reference cant be used if one wants to perform gain calibration ? [Bob]  You can still use the internal reference, you just can't over-range the PGA.

b) Can one bypass the PGA and perform gain calibration with +/-2.5V supply and internal reference? [Bob] See my example above.

c) Does the gain calibration need to be performed for each channel? One will need  to manage  the calibration coefficients for each channel. [Bob] This is difficult to answer without seeing your schematic.  First you have to determine if calibration is even necessary in the first place.  If it is required and if you had 4 different input with 4 different voltage dividers, then calibration of each input channel may need to be required.  Before doing all this effort you need to determine if you really need to calibrate or if the error is acceptable.

d) Is the FSC default settings different for each channel as well as each PGA setting? [Bob] The factory calibration is not channel specific and will only change value when changing the PGA gain.