Hello TI Team,
We are using ADC12DJ3200 connected to ARRIA 10 FPGA in JMODE1(16 lanes). We are operating ADC with 4.2GHz(lane rate = 4.2GHz) and 6 GHz(lane rate = 6GHz) sampling clock.
When we are using 6GHz sampling clock, all JESD lanes in FPGA are able to recover the clock from incoming data and so JESD link is up and able to capture the input RF data.
But when ADC is operating with 4.2GHz sampling clock one JESD receiver lane in FPGA is not able to recover the clock from incoming data.
Please suggest some solution to debug this issue.
JESD parameters used:
JMODE = 1
K = 5
Thanks and regard
Shyna
