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DAC37J84: PLL Instability at Low Temperature

kevin priest
Prodigy 160 points
Part Number: DAC37J84
Other Parts Discussed in Thread: LMK04828

Currently our DAC is setup to use the CLK PLL to generate a 1.2GHz sample clock from a 600MHz input clock. At room temperature the DAC appears to put out a normal tone, however, once we start dropping the temperature in the chamber spurs at a 45KHz offest (and harmonics) start to appear and grow in amplitude. The images attached is at -39C. If we do not use the CLK PLL and sample with just our incoming 600MHz clock, there are no spurs. It appears that the CLK PLL has some instability. We tried lowering the charge pump current from 1mA to 500uA, but did not observe any change. The VCO is set to 4.8GHz, Prescaler at 4, M=2, N=1.

No Clock PLL, tone at 6MHz

With Clock PLL, tone at 261MHz ( spurs will also show up with a 6MHz tone just the same).

  • 0
    TI__Guru* 78174 points

    Hello,

    The DAC37J84 have the VCO = 4800MHz tested across temperature with the following settings. 

    You may notice that the VCO = 4800MHz has pll_vcoiture = 11 and pll_vco = 26. Please double check if you have the proper setting. 

    If problem persists after double checking, you may also adjust pll_vco code up and down by +/-1, +/-2, etc to see if it helps with the lock range. 

    Please advise the reading of the 0x31 and 0x6C register of the PLL lock status. For the 0x6C register, please be sure to clear the alarm before reading back. Clearing the alarm is writing zeros first.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 160 points

    We verified that the pll_vcosel, pll_vco, and pll_vcitune settings are the same as in the table. We even read back the memin_pll_lfvolt register and it reads '100'. We tried writing to the DAC through our FPGA to change the pll_vco setting from 26 decimal to 27 and 28 as you said, but the DAC crashes when we do this. By crashes the 261MHz single tone just goes away and never recovers. Can PLL registers not be written to and changed on the fly?

  • 0 in reply to kevin priest
    TI__Guru* 78174 points

    Hello,

    The PLL_VCO code indeed changes the VCO characteristics and may sometimes cause the PLL to go unlock when changed on the fly. If you can change the PLL_VCO code at the boot-up of the DAC and then start the temperature testing, this will give the most stable result.

    I reviewed your unstable DAC output screen shot again and noticed that the offset spur is at 45kHz. This is a rather low frequency modulation that no components within the DAC (i.e. R/L/C) can achieve such oscillation. Typically, when this occurs, this is due to the ground bounce or PLL/VCO power supply bounce that may be coupled from any DC/DC power supplies. Please check the following:

    1. all the DC/DC switching converters that is powering the DAC. Measure the exact frequencies of each power converter.

    2. most likely the 45kHz is not the switching frequency of the power converter, but rather, it is caused by the beating (i.e. two DC/DC converters modulating to form 45kHz). This is the reason that you need to measure the exact frequencies of each power supplies. Note the converters that may cause the modulation and provide additional filtering.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 160 points

    There are three switching power supplies which supply the DAC. They all switch at 500kHz and share the same clock, although not the same phase. Since they are synchronized together, they should not produce a beat frequency. Nevertheless I will check them again to make sure none of them have fallen out of lock to the 500KHz clock. 

  • 0 in reply to kevin priest
    Prodigy 160 points

    After further investigation, we have determined the real source of the problem is coming from the LMK04828 chips which supply the 600MHz clocks to the DACs. There appears to be possibly an injection locking problem between LMKs which is causing them to create the 45Khz spur. I will open a ticket on the clocking forum.