Hi,
Is latency of pipeline ADC fixed value?
It is described in the spec column as TYP5 cycle.
On the other hand, it is described in the explanation as 4.5 cycles on both edges.
I believe this parameter is a value determined by the architecture. Does it change under special conditions?
It is described in the spec column as TYP5 cycle.
On the other hand, it is described in the explanation as 4.5 cycles on both edges.
I believe this parameter is a value determined by the architecture. Does it change under special conditions?
Since our customer is considering replacement from the SAR, it is an important consideration whether the timing of both edges can be used as a conversion start trigger of the SAR.
Thank you.
Hiroshi
