What it the CS select high time requirement for ADC128S102QML?
Is there any history of spurious incorrect outputs readings on some devices under normal operation?
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What it the CS select high time requirement for ADC128S102QML?
Is there any history of spurious incorrect outputs readings on some devices under normal operation?
Hello Michael,
We have not characterized the minimum time CSb must be asserted high to take effect, but the time is very low and well under 10 ns.
We have not seen any incidences of incorrect output readings that were not attributed to an application error.
Common issues we see:
-There must be a full 16 clock cycles with CSb low or the input register will not be updated and the previous programmed input will be sampled.
-Taking an unused input below or above the power rails with cause an error in the conversion of the input being sampled.
Let me know if you have any other questions.