Other Parts Discussed in Thread: DAC37J84, , DAC38J84, LMK04828
I am using the TSW14J56EVM and DAC37J84EVM. I have custom HDL code on the Arria V GZ FPGA on the TSW14J56EVM set for link configuration parameters LMFS =4442, K = 10, and N/N' = 16. I am programming the DAC37J84 using the DAC3XJ8X GUI v.1.2.
On the Quick Start tab, I select the appropriate device, on-board clock, 4 lanes, and interpolation of 4 as shown below. My custom HDL code is set to run off the 184.32MHz clock, and everything should be hunky dory for the handshake between the boards.
When I go to the DAC3XJ8X Control tab, and select the JESD Block is where things start to get wonky. I want to modify the link parameters as listed above, with LMFS = 4442, K = 10, and N/N' = 16. The image below is how the setup appears to me before